diff --git a/transcript b/transcript new file mode 100644 index 0000000..a4d90bf --- /dev/null +++ b/transcript @@ -0,0 +1,14 @@ +# // Questa Sim-64 +# // Version 2019.4 linux_x86_64 Oct 15 2019 +# // +# // Copyright 1991-2019 Mentor Graphics Corporation +# // All Rights Reserved. +# // +# // QuestaSim and its associated documentation contain trade +# // secrets and commercial or financial information that are the property of +# // Mentor Graphics Corporation and are privileged, confidential, +# // and exempt from disclosure under the Freedom of Information Act, +# // 5 U.S.C. Section 552. Furthermore, this information +# // is prohibited from disclosure under the Trade Secrets Act, +# // 18 U.S.C. Section 1905. +# // diff --git a/uebung_projekt/hdl_src/sv/fram.sv b/uebung_projekt/hdl_src/sv/fram.sv index 553c71e..1b9dae5 100644 --- a/uebung_projekt/hdl_src/sv/fram.sv +++ b/uebung_projekt/hdl_src/sv/fram.sv @@ -53,13 +53,13 @@ module spi(bus.spi_port b, fram_if.fram_port_top i); if(FRAM_go == 1) clk_cntr <= clk_cntr + 1; - if(clk_cntr > 50 && FRAM_RW == 1'h1) begin + if(clk_cntr > 250 && FRAM_RW == 1'h1) begin b.spi_read <= FRAM_DATA_OUT[1:0]; FRAM_go <= 1'h0; FRAM_RW <= 1'h0; clk_cntr <= 0; end - else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin + else if(clk_cntr > 250 && FRAM_RW == 1'h0) begin FRAM_go <= 1'h0; clk_cntr <= 0; end diff --git a/uebung_projekt/simulationsscripts/wave.do b/uebung_projekt/simulationsscripts/wave.do index f74df85..eb15692 100644 --- a/uebung_projekt/simulationsscripts/wave.do +++ b/uebung_projekt/simulationsscripts/wave.do @@ -5,12 +5,13 @@ add wave -noupdate -radix binary /top_tb/t1/fpga_bus/dip add wave -noupdate -radix binary /top_tb/stim_clock_if/clk add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer -add wave -noupdate -radix binary /top_tb/t1/s/FRAM_Adr +add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_Adr add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr -add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_IN -add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_OUT +add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_IN +add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_OUT add wave -noupdate -radix binary /top_tb/t1/f/mosi add wave -noupdate -radix binary /top_tb/t1/f/sclk +add wave -noupdate -radix binary /top_tb/t1/fpga_bus/spi_read TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {0 ns} 0} quietly wave cursor active 0 diff --git a/uebung_projekt/transcript b/uebung_projekt/transcript index c4a3443..4dc47b3 100644 --- a/uebung_projekt/transcript +++ b/uebung_projekt/transcript @@ -12,16 +12,18 @@ # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // -do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl +do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl # # create workspace +# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. +# ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # vmap work ./work # Modifying modelsim.ini # # Compile sv-Designfiles # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # -- Compiling interface led_if # -- Compiling interface dip_if @@ -30,19 +32,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Top level modules: # --none-- -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # -- Compiling module stimuli # # Top level modules: # stimuli -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # -- Compiling module top # -- Compiling interface bus @@ -51,66 +53,66 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Top level modules: # top -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # -- Compiling module top_tb # # Top level modules: # top_tb -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # -- Compiling module timer # # Top level modules: # timer -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # -- Compiling module SPI_Master # # Top level modules: # SPI_Master -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # -- Compiling module SPI_Master_With_Single_CS # # Top level modules: # SPI_Master_With_Single_CS -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # -- Compiling module FRAM # # Top level modules: # FRAM -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # -- Compiling module spi # # Top level modules: # spi -# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # Run Simulation # vsim -cvg63 -voptargs=""+acc"" top_tb -# Start time: 14:04:53 on Jun 15,2023 +# Start time: 14:45:51 on Jun 15,2023 # ** Note: (vsim-3812) Design is being optimized... # ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)". # Loading sv_std.std @@ -129,10 +131,11 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # Loading work.SPI_Master(fast) # Loading work.parallelport(fast) # Loading work.stimuli(fast) -do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl +do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl # # create workspace # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. +# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # vmap work ./work @@ -140,7 +143,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Compile sv-Designfiles # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # -- Compiling interface led_if # -- Compiling interface dip_if @@ -149,19 +152,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Top level modules: # --none-- -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # -- Compiling module stimuli # # Top level modules: # stimuli -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # -- Compiling module top # -- Compiling interface bus @@ -170,68 +173,68 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Top level modules: # top -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # -- Compiling module top_tb # # Top level modules: # top_tb -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # -- Compiling module timer # # Top level modules: # timer -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # -- Compiling module SPI_Master # # Top level modules: # SPI_Master -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # -- Compiling module SPI_Master_With_Single_CS # # Top level modules: # SPI_Master_With_Single_CS -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # -- Compiling module FRAM # # Top level modules: # FRAM -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:11:54 on Jun 15,2023 +# Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # -- Compiling module spi # # Top level modules: # spi -# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # Run Simulation -# End time: 14:11:55 on Jun 15,2023, Elapsed time: 0:07:02 -# Errors: 12, Warnings: 1 +# End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27 +# Errors: 3, Warnings: 2 # vsim -cvg63 -voptargs=""+acc"" top_tb -# Start time: 14:11:55 on Jun 15,2023 +# Start time: 14:48:18 on Jun 15,2023 # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # Loading sv_std.std # Loading work.top_tb(fast) @@ -249,14 +252,13 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # Loading work.SPI_Master(fast) # Loading work.parallelport(fast) # Loading work.stimuli(fast) -# Can't move the Now cursor. -# Can't move the Now cursor. add wave -position insertpoint \ -sim:/top_tb/t1/f/mosi -do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl +sim:/top_tb/t1/fpga_bus/spi_read +do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl # # create workspace # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. +# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # vmap work ./work @@ -264,7 +266,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Compile sv-Designfiles # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:00 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # -- Compiling interface led_if # -- Compiling interface dip_if @@ -273,19 +275,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Top level modules: # --none-- -# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:00 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # -- Compiling module stimuli # # Top level modules: # stimuli -# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:00 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # -- Compiling module top # -- Compiling interface bus @@ -294,189 +296,69 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # # Top level modules: # top -# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:00 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # -- Compiling module top_tb # # Top level modules: # top_tb -# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:00 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # -- Compiling module timer # # Top level modules: # timer -# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:01 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # -- Compiling module SPI_Master # # Top level modules: # SPI_Master -# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:01 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # -- Compiling module SPI_Master_With_Single_CS # # Top level modules: # SPI_Master_With_Single_CS -# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:01 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # -- Compiling module FRAM # # Top level modules: # FRAM -# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:19:01 on Jun 15,2023 +# Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # -- Compiling module spi # # Top level modules: # spi -# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00 +# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # Run Simulation -# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:07:06 -# Errors: 12, Warnings: 1 +# End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49 +# Errors: 1, Warnings: 2 # vsim -cvg63 -voptargs=""+acc"" top_tb -# Start time: 14:19:01 on Jun 15,2023 -# ** Note: (vsim-8009) Loading existing optimized design _opt -# Loading sv_std.std -# Loading work.top_tb(fast) -# Loading work.led_if(fast) -# Loading work.dip_if(fast) -# Loading work.fram_if(fast) -# Loading work.clock_if(fast) -# Loading work.top(fast) -# Loading work.bus(fast) -# Loading work.timer(fast) -# Loading work.steuerung(fast) -# Loading work.spi(fast) -# Loading work.FRAM(fast) -# Loading work.SPI_Master_With_Single_CS(fast) -# Loading work.SPI_Master(fast) -# Loading work.parallelport(fast) -# Loading work.stimuli(fast) -do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl -# -# create workspace -# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. -# ** Warning: (vlib-34) Library already exists at "work". -# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 -# vmap work ./work -# Modifying modelsim.ini -# -# Compile sv-Designfiles -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv -# -- Compiling interface led_if -# -- Compiling interface dip_if -# -- Compiling interface fram_if -# -- Compiling interface clock_if -# -# Top level modules: -# --none-- -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv -# -- Compiling module stimuli -# -# Top level modules: -# stimuli -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv -# -- Compiling module top -# -- Compiling interface bus -# -- Compiling module parallelport -# -- Compiling module steuerung -# -# Top level modules: -# top -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv -# -- Compiling module top_tb -# -# Top level modules: -# top_tb -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv -# -- Compiling module timer -# -# Top level modules: -# timer -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv -# -- Compiling module SPI_Master -# -# Top level modules: -# SPI_Master -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv -# -- Compiling module SPI_Master_With_Single_CS -# -# Top level modules: -# SPI_Master_With_Single_CS -# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:07 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv -# -- Compiling module FRAM -# -# Top level modules: -# FRAM -# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:01 -# Errors: 0, Warnings: 0 -# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 -# Start time: 14:22:08 on Jun 15,2023 -# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv -# -- Compiling module spi -# -# Top level modules: -# spi -# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# -# Run Simulation -# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:03:07 -# Errors: 5, Warnings: 1 -# vsim -cvg63 -voptargs=""+acc"" top_tb -# Start time: 14:22:08 on Jun 15,2023 -# ** Note: (vsim-3813) Design is being optimized due to module recompilation... +# Start time: 14:51:07 on Jun 15,2023 +# ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading sv_std.std # Loading work.top_tb(fast) # Loading work.led_if(fast) @@ -493,3 +375,5 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript # Loading work.SPI_Master(fast) # Loading work.parallelport(fast) # Loading work.stimuli(fast) +# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16 +# Errors: 3, Warnings: 0 diff --git a/uebung_projekt/vsim.wlf b/uebung_projekt/vsim.wlf index ec60ce0..973ed64 100644 Binary files a/uebung_projekt/vsim.wlf and b/uebung_projekt/vsim.wlf differ diff --git a/uebung_projekt/work/@_opt1/_lib.qdb b/uebung_projekt/work/@_opt1/_lib.qdb new file mode 100644 index 0000000..0b1f4a0 Binary files /dev/null and b/uebung_projekt/work/@_opt1/_lib.qdb differ diff --git a/uebung_projekt/work/@_opt1/_lib1_0.qdb b/uebung_projekt/work/@_opt1/_lib1_0.qdb new file mode 100644 index 0000000..9415f33 Binary files /dev/null and b/uebung_projekt/work/@_opt1/_lib1_0.qdb differ diff --git a/uebung_projekt/work/@_opt1/_lib1_0.qpg b/uebung_projekt/work/@_opt1/_lib1_0.qpg new file mode 100644 index 0000000..f497b7d Binary files /dev/null and b/uebung_projekt/work/@_opt1/_lib1_0.qpg differ diff --git a/uebung_projekt/work/@_opt1/_lib1_0.qtl b/uebung_projekt/work/@_opt1/_lib1_0.qtl new file mode 100644 index 0000000..883ac17 Binary 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b/uebung_projekt/work/@_opt1/_lib5_0.qdb differ diff --git a/uebung_projekt/work/@_opt1/_lib5_0.qpg b/uebung_projekt/work/@_opt1/_lib5_0.qpg new file mode 100644 index 0000000..2161b2c Binary files /dev/null and b/uebung_projekt/work/@_opt1/_lib5_0.qpg differ diff --git a/uebung_projekt/work/@_opt1/_lib5_0.qtl b/uebung_projekt/work/@_opt1/_lib5_0.qtl new file mode 100644 index 0000000..84cba6e Binary files /dev/null and b/uebung_projekt/work/@_opt1/_lib5_0.qtl differ diff --git a/uebung_projekt/work/_info b/uebung_projekt/work/_info index ac679df..b877e41 100644 --- a/uebung_projekt/work/_info +++ b/uebung_projekt/work/_info @@ -10,389 +10,400 @@ z2 cModel Technology Z0 d/users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt T_opt -Z1 !s110 1686831728 +!s110 1686831728 V2L38BN@acDd:OB=HL_FC32 -04 6 4 work top_tb fast 0 +Z1 04 6 4 work top_tb fast 0 =1-005056b42dc6-648b0270-7d119-559d -o-quiet -auto_acc_if_foreign -work work +acc -Z2 tCvgOpt 0 +Z2 o-quiet -auto_acc_if_foreign -work work +acc +Z3 tCvgOpt 0 n@_opt -OL;O;2019.4;69 +Z4 OL;O;2019.4;69 +R0 +T_opt1 +!s110 1686833298 +V4N01Y?dc<]WhdSf73Ue?91 +R1 +=1-005056b42dc6-648b0892-563db-611e +R2 +R3 +n@_opt1 +R4 +R0 Ybus -Z3 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92 -Z4 !s110 1686831727 +Z5 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92 +Z6 !s110 1686833462 !i10b 1 !s100 T;581z6K]3OXG=KOJdK4G2 !s11b Dj[TOJX9onk[mCamXbz9c3 I<3_5F:_4Ri@f;?1:3BJf=2 -Z5 VDg1SIo80bB@j0V0VzS_@n1 +Z7 VDg1SIo80bB@j0V0VzS_@n1 S1 -R0 -Z6 w1686830281 -Z7 8./hdl_src/sv/top_level.sv -Z8 F./hdl_src/sv/top_level.sv +Z8 d/users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt +Z9 w1686832439 +Z10 8./hdl_src/sv/top_level.sv +Z11 F./hdl_src/sv/top_level.sv !i122 -1 L0 15 -Z9 OL;L;2019.4;69 +Z12 OL;L;2019.4;69 r1 !s85 0 31 -Z10 !s108 1686831727.000000 -Z11 !s107 ./hdl_src/sv/top_level.sv| -Z12 !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_level.sv| +Z13 !s108 1686833462.000000 +Z14 !s107 ./hdl_src/sv/top_level.sv| +Z15 !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_level.sv| !i113 0 -Z13 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -R2 +Z16 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +R3 Yclock_if -R3 -R4 +R5 +R6 !i10b 1 -!s100 iND9Vz2l5W=c=U@m@mlh@>YnK82 !s11b oJPC4U0:1B^QG:cZC>8A:1 -IOQJeZ`mU83 +R7 S1 -R0 -Z14 w1686314964 -Z15 8./hdl_src/sv/interface.sv -Z16 F./hdl_src/sv/interface.sv +R8 +Z17 w1686832912 +Z18 8./hdl_src/sv/interface.sv +Z19 F./hdl_src/sv/interface.sv !i122 -1 -L0 60 -R9 +L0 61 +R12 r1 !s85 0 31 -R10 -Z17 !s107 ./hdl_src/sv/interface.sv| -Z18 !s90 -reportprogress|300|-work|work|./hdl_src/sv/interface.sv| -!i113 0 R13 -R2 -Ydip_if -R3 -R4 -!i10b 1 -!s100 lPioFG@0T7j3gKFQYYe8W0 -!s11b @Hfo8VJnf;PXXPSgXE44V1 -I@=49][3E;]nafb=5@ka:a0 -R5 -S1 -R0 -R14 -R15 +Z20 !s107 ./hdl_src/sv/interface.sv| +Z21 !s90 -reportprogress|300|-work|work|./hdl_src/sv/interface.sv| +!i113 0 R16 -!i122 -1 -L0 33 -R9 -r1 -!s85 0 -31 -R10 +R3 +Ydip_if +R5 +R6 +!i10b 1 +!s100 Ho3QlAW4UmzOWF^R8D3 +!s11b JgIFT9[W_4_O1 -!s11b djVBMKk[@Wh5FXIDGlUF[2 -I`agi[9j3c9e5gcFWSVSH51 -R5 -S1 -R0 -R14 -R15 -R16 +R19 !i122 -1 L0 21 -R9 +R12 r1 !s85 0 31 -R10 -R17 -R18 -!i113 0 R13 -R2 -vparallelport +R20 +R21 +!i113 0 +R16 R3 -R4 +vparallelport +R5 +R6 !i10b 1 !s100 Oh9lLSH=`_Q:=@41ZzlcY2 !s11b k21ML[34E18n]@g]EG:g02 I;1_EJNiVm[nDB?57=nXOD3 -R5 -S1 -R0 -R6 R7 +S1 R8 +R9 +R10 +R11 !i122 -1 L0 30 -R9 +R12 r1 !s85 0 31 -R10 -R11 -R12 -!i113 0 R13 -R2 -vspi +R14 +R15 +!i113 0 +R16 R3 -R1 -!i10b 1 -!s100 FWg;A^hM6Xk;TFJMgza]m2 -!s11b NBC7eT]a7]iC:n6DXhW[e0 -Ilbh>SdZV4bSDzE22EQIiC3 +vspi R5 +R6 +!i10b 1 +!s100 GPbXMO8=ajXa5d]lGaVmH2 +!s11b AgHIb1 +R7 S1 -R0 -w1686830667 +R8 +w1686833271 8./hdl_src/sv/fram.sv F./hdl_src/sv/fram.sv !i122 -1 L0 4 -R9 +R12 r1 !s85 0 31 -!s108 1686831728.000000 +R13 !s107 ./hdl_src/sv/fram.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/fram.sv| !i113 0 -R13 -R2 -vSPI_Master +R16 R3 -R4 +vSPI_Master +R5 +R6 !i10b 1 !s100 LNaIK]EJb:HMhCL_bcUOT2 !s11b RZ[UYHW;Fa4LhmckzB[DGbebG_Mk0W]hI8XCQ?k0 !s11b WKleG=JcKL4FgO@TP[IO[1 IE`WCa5G2QlghM9EX[<1dS3 -R5 -S1 -R0 -R6 R7 +S1 R8 -!i122 -1 -R20 R9 +R10 +R11 +!i122 -1 +R23 +R12 r1 !s85 0 31 -R10 -R11 -R12 -!i113 0 R13 -R2 -vstimuli +R14 +R15 +!i113 0 +R16 R3 -R4 +vstimuli +R5 +R6 !i10b 1 !s100 ?c5GG;9B8k3 IEenLI0W00diXD61Ele2;U0 -R5 +R7 S1 -R0 -w1686831703 +R8 +R9 8./hdl_src/sv/timer.sv F./hdl_src/sv/timer.sv !i122 -1 L0 19 -R9 +R12 r1 !s85 0 31 -R10 +R13 !s107 ./hdl_src/sv/timer.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/timer.sv| !i113 0 -R13 -R2 -vtop +R16 R3 -R4 +vtop +R5 +R6 !i10b 1 !s100 6?3aiGY1NTOnA[jU;ZnEa3 !s11b =zPVnM;Zm1L1Ig2finB;E2 I^g60QFGiK:2b=KZhX2 !s11b jcE]a:O3cJ<=CdGZ:MgQ62 IbRb[2DAWSb2IUOHB[hFz:2 -R5 +R7 S1 -R0 -w1686315659 +R8 +R9 8./hdl_src/sv/top_tb.sv F./hdl_src/sv/top_tb.sv !i122 -1 -R19 -R9 +R22 +R12 r1 !s85 0 31 -R10 +R13 !s107 ./hdl_src/sv/top_tb.sv| !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_tb.sv| !i113 0 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