From 2624055082b6c1fad941c7da3d5ef109c61f51e7 Mon Sep 17 00:00:00 2001
From: Alexander Mueller <muelleral82290@th-nuernberg.de>
Date: Thu, 15 Jun 2023 10:13:12 +0000
Subject: [PATCH] =?UTF-8?q?Dateien=20hochladen=20nach=20=E2=80=9E=E2=80=9C?=
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---
 interface.sv | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 interface.sv

diff --git a/interface.sv b/interface.sv
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+//------------------------------------------------------
+//                                                        
+//  File          :  interface.sv
+//  Related Files :                                                     
+//  Author(s)     :  Mueller                              
+//  Email         :  muelleral82290@th-nuernberg.de       
+//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
+//  Notes         :  Stimuli Modul 
+//
+//------------------------------------------------------
+//                   History    
+//------------------------------------------------------
+//    Version| Author   | Mod. Date  | Changes Made:
+//    v1.00  | Mueller  | 11/05/2023 | first code
+//------------------------------------------------------
+//eoh
+
+
+//interface for LED
+//reg [2:0]rbg stores rgb values that depend on dip[3:2]
+interface led_if();
+
+	logic [2:0]rgb;
+
+	modport led_port_stim(input rgb);
+	modport led_port_top(output rgb);
+	
+
+endinterface : led_if
+
+//interface for DIPSCHALER
+// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
+interface dip_if();
+
+	logic [3:0]dip;
+
+	modport dip_port_stim(output dip);
+	modport dip_port_top(input dip);
+
+endinterface : dip_if
+
+//interface for FRAM
+// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
+// clk -> system clock / timer
+// miso -> testbench output
+// mosi -> testbench input
+interface fram_if();
+
+	logic ss;
+	logic mosi;
+	logic miso;
+	logic sclk;
+
+	modport fram_port_stim(input mosi, sclk, ss, output miso);
+	modport fram_port_top(output mosi, sclk, ss, input miso);
+
+endinterface : fram_if
+
+//testbenchclock replaces the oscillator on the board
+interface clock_if();
+
+	logic clk;
+
+	modport clock_port_stim(output clk);
+	modport clock_port_top(input clk);
+
+endinterface : clock_if
+
+