From 5213d9b6eb687797b7d12daec1020ea78aaa0b40 Mon Sep 17 00:00:00 2001 From: Alexander Mueller Date: Thu, 15 Jun 2023 10:17:40 +0000 Subject: [PATCH] =?UTF-8?q?Dateien=20hochladen=20nach=20=E2=80=9E=E2=80=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- top_level.sv | 109 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 top_level.sv diff --git a/top_level.sv b/top_level.sv new file mode 100644 index 0000000..e0105fa --- /dev/null +++ b/top_level.sv @@ -0,0 +1,109 @@ +// Definition of top level +module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c); + + // Initialisation of bus + bus fpga_bus(); + + // Initialisation of modules + timer t(fpga_bus, c); + steuerung st(fpga_bus, l); + spi s(fpga_bus, f); + parallelport p(fpga_bus, d); +endmodule : top + +// Definition of bus interface +interface bus(); + // bus wires + logic clk; // clock + logic timer; + logic [3:0]dip; + logic [1:0]spi_read; + + // modports from modules pov + modport timer_port(input dip, output timer, clk); //dip[0] + modport parallel_port(output dip); + modport steuerung_port(input dip, timer, spi_read); //dip[3:0] / spi_read[1:0] + modport spi_port(input dip, timer, output spi_read); //spi_read[1:0] +endinterface : bus + +// Definition of parallelport +module parallelport(bus.parallel_port b, dip_if.dip_port_top d); + //b.dip <= d.dip; +endmodule + +module spi(bus.spi_port b, fram_if.fram_port_top i); + /*... + b.dip[3:0], b.timer, b.spi_read[1:0] + i.ss, i.mosi, i.miso, i.sclk + ...*/ +endmodule + +module timer(bus.timer_port b, clock_if.clock_port_top i); + /*... + b.clk, b.dip[0], b.timer + i.clk + ...*/ +endmodule + +module steuerung(bus.steuerung_port b, led_if.led_port_top i); + /*... + b.dip[3:0], b.timer, b.spi_read[1:0] + i.rgb[2:0] + ...*/ +endmodule + +/* +_______________________________________________________________________________________________________________ +Testbench + __________________ ___________________ + | | | | + | DIP-Schalter | | FRAM-Speicher | + | | | | + |__________________| |___________________| + | | +____________________________|________________________________________________________________|_________________ +Toplevel | | + | | + dip[3:0]-->| |<--mosi, miso, sclk, ss + | | + ________|_________ ________|__________ + | | | | + | Parallelport | | SPI-Schnittstelle | + | | | & FRAM-Kontroller | + |__________________| |___________________| + | | + | | + dip[3:0]-->| |<--dip[3:0], timer, spi_read[1:0] + | | + | | + ---------------------------------------------------------------------BUS + | | + | | + dip[0], clk, timer-->| |<--dip[3:0], timer, spi_read[1:0] + | | + ________|_________ ___________________ ________|__________ + | | | | | | + | Timer | | Oszillator-Takt | | Ampel-Steuerung | + | | | (auf Board) | | | + |__________________| |___________________| |___________________| + | | | + | | | + clk-->------------------------------ |<--rgb[2:0] + | | +____________________________|________________________________________________________________|___________________ + | | + ________|_________ ________|__________ + | | | | + | Takt | | RGB-LED | + | (der Testbench) | | | + |__________________| |___________________| + + +__________________________________________________________________________________________________________________ + +*/ + + + + +