|
|
|
|
|
|
|
|
logic [1:0]spi_read; |
|
|
logic [1:0]spi_read; |
|
|
|
|
|
|
|
|
// modports from modules pov |
|
|
// modports from modules pov |
|
|
modport timer_port(input dip, output timer, clk); //dip[0] |
|
|
|
|
|
|
|
|
modport timer_port(input dip, output timer, clk); //dip[0] |
|
|
modport parallel_port(output dip); |
|
|
modport parallel_port(output dip); |
|
|
modport steuerung_port(input dip, timer, spi_read); //dip[3:0] / spi_read[1:0] |
|
|
|
|
|
modport spi_port(input dip, timer, output spi_read); //spi_read[1:0] |
|
|
|
|
|
|
|
|
modport steuerung_port(input dip, timer, clk, spi_read); //dip[3:0] / spi_read[1:0] |
|
|
|
|
|
modport spi_port(input dip, timer, clk, output spi_read); //spi_read[1:0] |
|
|
endinterface : bus |
|
|
endinterface : bus |
|
|
|
|
|
|
|
|
// Definition of parallelport |
|
|
// Definition of parallelport |