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Niklas Boese 2023-06-15 12:34:33 +00:00
parent d8f3dff5cf
commit f6acd4c2fb
1 changed files with 3 additions and 3 deletions
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top_level.sv
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@ -20,10 +20,10 @@ interface bus();
logic [1:0]spi_read;
// modports from modules pov
modport timer_port(input dip, output timer, clk); //dip[0]
modport timer_port(input dip, output timer, clk); //dip[0]
modport parallel_port(output dip);
modport steuerung_port(input dip, timer, spi_read); //dip[3:0] / spi_read[1:0]
modport spi_port(input dip, timer, output spi_read); //spi_read[1:0]
modport steuerung_port(input dip, timer, clk, spi_read); //dip[3:0] / spi_read[1:0]
modport spi_port(input dip, timer, clk, output spi_read); //spi_read[1:0]
endinterface : bus
// Definition of parallelport