25 changed files with 385 additions and 295 deletions
--- a/14
+++ b/14
@ -1,14 +0,0 @@
-# //  Questa Sim-64
-# //  Version 2019.4 linux_x86_64 Oct 15 2019
-# //
-# //  Copyright 1991-2019 Mentor Graphics Corporation
-# //  All Rights Reserved.
-# //
-# //  QuestaSim and its associated documentation contain trade
-# //  secrets and commercial or financial information that are the property of
-# //  Mentor Graphics Corporation and are privileged, confidential,
-# //  and exempt from disclosure under the Freedom of Information Act,
-# //  5 U.S.C. Section 552. Furthermore, this information
-# //  is prohibited from disclosure under the Trade Secrets Act,
-# //  18 U.S.C. Section 1905.
-# //
--- a/uebung_projekt/hdl_src/sv/fram.sv
+++ b/uebung_projekt/hdl_src/sv/fram.sv
@ -53,13 +53,13 @@ module spi(bus.spi_port b, fram_if.fram_port_top i);
    if(FRAM_go == 1) 
      clk_cntr <= clk_cntr + 1;
    
-    if(clk_cntr > 250 && FRAM_RW == 1'h1) begin
+    if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
      b.spi_read <= FRAM_DATA_OUT[1:0];
      FRAM_go <= 1'h0;
      FRAM_RW <= 1'h0; 
      clk_cntr <= 0;
    end
-    else if(clk_cntr > 250 && FRAM_RW == 1'h0) begin
+    else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
      FRAM_go <= 1'h0;
      clk_cntr <= 0;
    end
--- a/uebung_projekt/simulationsscripts/wave.do
+++ b/uebung_projekt/simulationsscripts/wave.do
@ -5,13 +5,12 @@ add wave -noupdate -radix binary /top_tb/t1/fpga_bus/dip
 add wave -noupdate -radix binary /top_tb/stim_clock_if/clk
 add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk
 add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer
-add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_Adr
+add wave -noupdate -radix binary /top_tb/t1/s/FRAM_Adr
 add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr
-add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_IN
-add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_OUT
+add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_IN
+add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_OUT
 add wave -noupdate -radix binary /top_tb/t1/f/mosi
 add wave -noupdate -radix binary /top_tb/t1/f/sclk
-add wave -noupdate -radix binary /top_tb/t1/fpga_bus/spi_read
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 1} {0 ns} 0}
 quietly wave cursor active 0
--- a/uebung_projekt/transcript
+++ b/uebung_projekt/transcript
@ -12,18 +12,16 @@
 # //  is prohibited from disclosure under the Trade Secrets Act,
 # //  18 U.S.C. Section 1905.
 # //
-do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
+do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
 # 
 # create workspace
-# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
-# ** Warning: (vlib-34) Library already exists at "work".
 # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
 # vmap work ./work 
 # Modifying modelsim.ini
 # 
 #  Compile sv-Designfiles 
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:50 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
 # -- Compiling interface led_if
 # -- Compiling interface dip_if
@ -32,19 +30,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 # Top level modules:
 # 	--none--
-# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:50 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
 # -- Compiling module stimuli
 # 
 # Top level modules:
 # 	stimuli
-# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:50 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
 # -- Compiling module top
 # -- Compiling interface bus
@ -53,66 +51,66 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 # Top level modules:
 # 	top
-# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:50 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
 # -- Compiling module top_tb
 # 
 # Top level modules:
 # 	top_tb
-# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:51 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
 # -- Compiling module timer
 # 
 # Top level modules:
 # 	timer
-# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:51 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
 # -- Compiling module SPI_Master
 # 
 # Top level modules:
 # 	SPI_Master
-# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:51 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
 # -- Compiling module SPI_Master_With_Single_CS
 # 
 # Top level modules:
 # 	SPI_Master_With_Single_CS
-# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:51 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
 # -- Compiling module FRAM
 # 
 # Top level modules:
 # 	FRAM
-# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:45:51 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
 # -- Compiling module spi
 # 
 # Top level modules:
 # 	spi
-# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # 
 #  Run Simulation 
 # vsim -cvg63 -voptargs=""+acc"" top_tb 
-# Start time: 14:45:51 on Jun 15,2023
+# Start time: 14:04:53 on Jun 15,2023
 # ** Note: (vsim-3812) Design is being optimized...
 # ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
 # Loading sv_std.std
@ -131,11 +129,10 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # Loading work.SPI_Master(fast)
 # Loading work.parallelport(fast)
 # Loading work.stimuli(fast)
-do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
+do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
 # 
 # create workspace
 # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
-# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
 # ** Warning: (vlib-34) Library already exists at "work".
 # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
 # vmap work ./work 
@ -143,7 +140,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 #  Compile sv-Designfiles 
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
 # -- Compiling interface led_if
 # -- Compiling interface dip_if
@ -152,19 +149,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 # Top level modules:
 # 	--none--
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
 # -- Compiling module stimuli
 # 
 # Top level modules:
 # 	stimuli
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
 # -- Compiling module top
 # -- Compiling interface bus
@ -173,68 +170,68 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 # Top level modules:
 # 	top
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
 # -- Compiling module top_tb
 # 
 # Top level modules:
 # 	top_tb
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
 # -- Compiling module timer
 # 
 # Top level modules:
 # 	timer
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
 # -- Compiling module SPI_Master
 # 
 # Top level modules:
 # 	SPI_Master
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
 # -- Compiling module SPI_Master_With_Single_CS
 # 
 # Top level modules:
 # 	SPI_Master_With_Single_CS
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
 # -- Compiling module FRAM
 # 
 # Top level modules:
 # 	FRAM
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:48:17 on Jun 15,2023
+# Start time: 14:11:54 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
 # -- Compiling module spi
 # 
 # Top level modules:
 # 	spi
-# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # 
 #  Run Simulation 
-# End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
-# Errors: 3, Warnings: 2
+# End time: 14:11:55 on Jun 15,2023, Elapsed time: 0:07:02
+# Errors: 12, Warnings: 1
 # vsim -cvg63 -voptargs=""+acc"" top_tb 
-# Start time: 14:48:18 on Jun 15,2023
+# Start time: 14:11:55 on Jun 15,2023
 # ** Note: (vsim-3813) Design is being optimized due to module recompilation...
 # Loading sv_std.std
 # Loading work.top_tb(fast)
@ -252,13 +249,14 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # Loading work.SPI_Master(fast)
 # Loading work.parallelport(fast)
 # Loading work.stimuli(fast)
+# Can't move the Now cursor.
+# Can't move the Now cursor.
 add wave -position insertpoint  \
-sim:/top_tb/t1/fpga_bus/spi_read
-do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
+sim:/top_tb/t1/f/mosi
+do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
 # 
 # create workspace
 # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
-# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
 # ** Warning: (vlib-34) Library already exists at "work".
 # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
 # vmap work ./work 
@ -266,7 +264,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 #  Compile sv-Designfiles 
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:00 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
 # -- Compiling interface led_if
 # -- Compiling interface dip_if
@ -275,19 +273,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 # Top level modules:
 # 	--none--
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:00 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
 # -- Compiling module stimuli
 # 
 # Top level modules:
 # 	stimuli
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:00 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
 # -- Compiling module top
 # -- Compiling interface bus
@ -296,69 +294,189 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # 
 # Top level modules:
 # 	top
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:00 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
 # -- Compiling module top_tb
 # 
 # Top level modules:
 # 	top_tb
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:00 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
 # -- Compiling module timer
 # 
 # Top level modules:
 # 	timer
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:01 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
 # -- Compiling module SPI_Master
 # 
 # Top level modules:
 # 	SPI_Master
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:01 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
 # -- Compiling module SPI_Master_With_Single_CS
 # 
 # Top level modules:
 # 	SPI_Master_With_Single_CS
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:01 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
 # -- Compiling module FRAM
 # 
 # Top level modules:
 # 	FRAM
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
-# Start time: 14:51:02 on Jun 15,2023
+# Start time: 14:19:01 on Jun 15,2023
 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
 # -- Compiling module spi
 # 
 # Top level modules:
 # 	spi
-# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
+# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
 # Errors: 0, Warnings: 0
 # 
 #  Run Simulation 
-# End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
-# Errors: 1, Warnings: 2
+# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:07:06
+# Errors: 12, Warnings: 1
 # vsim -cvg63 -voptargs=""+acc"" top_tb 
-# Start time: 14:51:07 on Jun 15,2023
-# ** Note: (vsim-8009) Loading existing optimized design _opt1
+# Start time: 14:19:01 on Jun 15,2023
+# ** Note: (vsim-8009) Loading existing optimized design _opt
+# Loading sv_std.std
+# Loading work.top_tb(fast)
+# Loading work.led_if(fast)
+# Loading work.dip_if(fast)
+# Loading work.fram_if(fast)
+# Loading work.clock_if(fast)
+# Loading work.top(fast)
+# Loading work.bus(fast)
+# Loading work.timer(fast)
+# Loading work.steuerung(fast)
+# Loading work.spi(fast)
+# Loading work.FRAM(fast)
+# Loading work.SPI_Master_With_Single_CS(fast)
+# Loading work.SPI_Master(fast)
+# Loading work.parallelport(fast)
+# Loading work.stimuli(fast)
+do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
+# 
+# create workspace
+# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt".  Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
+# ** Warning: (vlib-34) Library already exists at "work".
+# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
+# vmap work ./work 
+# Modifying modelsim.ini
+# 
+#  Compile sv-Designfiles 
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv 
+# -- Compiling interface led_if
+# -- Compiling interface dip_if
+# -- Compiling interface fram_if
+# -- Compiling interface clock_if
+# 
+# Top level modules:
+# 	--none--
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv 
+# -- Compiling module stimuli
+# 
+# Top level modules:
+# 	stimuli
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv 
+# -- Compiling module top
+# -- Compiling interface bus
+# -- Compiling module parallelport
+# -- Compiling module steuerung
+# 
+# Top level modules:
+# 	top
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv 
+# -- Compiling module top_tb
+# 
+# Top level modules:
+# 	top_tb
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv 
+# -- Compiling module timer
+# 
+# Top level modules:
+# 	timer
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv 
+# -- Compiling module SPI_Master
+# 
+# Top level modules:
+# 	SPI_Master
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv 
+# -- Compiling module SPI_Master_With_Single_CS
+# 
+# Top level modules:
+# 	SPI_Master_With_Single_CS
+# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:07 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv 
+# -- Compiling module FRAM
+# 
+# Top level modules:
+# 	FRAM
+# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 0
+# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
+# Start time: 14:22:08 on Jun 15,2023
+# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv 
+# -- Compiling module spi
+# 
+# Top level modules:
+# 	spi
+# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# 
+#  Run Simulation 
+# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:03:07
+# Errors: 5, Warnings: 1
+# vsim -cvg63 -voptargs=""+acc"" top_tb 
+# Start time: 14:22:08 on Jun 15,2023
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
 # Loading sv_std.std
 # Loading work.top_tb(fast)
 # Loading work.led_if(fast)
@ -375,5 +493,3 @@ do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/c
 # Loading work.SPI_Master(fast)
 # Loading work.parallelport(fast)
 # Loading work.stimuli(fast)
-# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
-# Errors: 3, Warnings: 0
--- a/uebung_projekt/vsim.wlf
+++ b/uebung_projekt/vsim.wlf
--- a/uebung_projekt/work/@_opt1/_lib.qdb
+++ b/uebung_projekt/work/@_opt1/_lib.qdb
--- a/uebung_projekt/work/@_opt1/_lib1_0.qdb
+++ b/uebung_projekt/work/@_opt1/_lib1_0.qdb
--- a/uebung_projekt/work/@_opt1/_lib1_0.qpg
+++ b/uebung_projekt/work/@_opt1/_lib1_0.qpg
--- a/uebung_projekt/work/@_opt1/_lib1_0.qtl
+++ b/uebung_projekt/work/@_opt1/_lib1_0.qtl
--- a/uebung_projekt/work/@_opt1/_lib2_0.qdb
+++ b/uebung_projekt/work/@_opt1/_lib2_0.qdb
--- a/uebung_projekt/work/@_opt1/_lib2_0.qpg
+++ b/uebung_projekt/work/@_opt1/_lib2_0.qpg
--- a/uebung_projekt/work/@_opt1/_lib2_0.qtl
+++ b/uebung_projekt/work/@_opt1/_lib2_0.qtl
--- a/uebung_projekt/work/@_opt1/_lib3_0.qdb
+++ b/uebung_projekt/work/@_opt1/_lib3_0.qdb
--- a/uebung_projekt/work/@_opt1/_lib3_0.qpg
+++ b/uebung_projekt/work/@_opt1/_lib3_0.qpg
--- a/uebung_projekt/work/@_opt1/_lib3_0.qtl
+++ b/uebung_projekt/work/@_opt1/_lib3_0.qtl
--- a/uebung_projekt/work/@_opt1/_lib4_0.qdb
+++ b/uebung_projekt/work/@_opt1/_lib4_0.qdb
--- a/uebung_projekt/work/@_opt1/_lib4_0.qpg
+++ b/uebung_projekt/work/@_opt1/_lib4_0.qpg
--- a/uebung_projekt/work/@_opt1/_lib4_0.qtl
+++ b/uebung_projekt/work/@_opt1/_lib4_0.qtl
--- a/uebung_projekt/work/@_opt1/_lib5_0.qdb
+++ b/uebung_projekt/work/@_opt1/_lib5_0.qdb
--- a/uebung_projekt/work/@_opt1/_lib5_0.qpg
+++ b/uebung_projekt/work/@_opt1/_lib5_0.qpg
--- a/uebung_projekt/work/@_opt1/_lib5_0.qtl
+++ b/uebung_projekt/work/@_opt1/_lib5_0.qtl
--- a/uebung_projekt/work/_info
+++ b/uebung_projekt/work/_info
@ -10,400 +10,389 @@ z2
 cModel Technology
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--- a/uebung_projekt/work/_lib.qdb
+++ b/uebung_projekt/work/_lib.qdb
--- a/uebung_projekt/work/_lib1_0.qdb
+++ b/uebung_projekt/work/_lib1_0.qdb
--- a/uebung_projekt/work/_lib1_0.qtl
+++ b/uebung_projekt/work/_lib1_0.qtl