# // Questa Sim-64 # // Version 2019.4 linux_x86_64 Oct 15 2019 # // # // Copyright 1991-2019 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl # # create workspace # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # vmap work ./work # Modifying modelsim.ini # # Compile sv-Designfiles # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # -- Compiling interface led_if # -- Compiling interface dip_if # -- Compiling interface fram_if # -- Compiling interface clock_if # # Top level modules: # --none-- # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # -- Compiling module stimuli # # Top level modules: # stimuli # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # -- Compiling module top # -- Compiling interface bus # -- Compiling module parallelport # -- Compiling module steuerung # # Top level modules: # top # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:50 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # -- Compiling module top_tb # # Top level modules: # top_tb # End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # -- Compiling module timer # # Top level modules: # timer # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # -- Compiling module SPI_Master # # Top level modules: # SPI_Master # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # -- Compiling module SPI_Master_With_Single_CS # # Top level modules: # SPI_Master_With_Single_CS # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # -- Compiling module FRAM # # Top level modules: # FRAM # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:45:51 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # -- Compiling module spi # # Top level modules: # spi # End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # Run Simulation # vsim -cvg63 -voptargs=""+acc"" top_tb # Start time: 14:45:51 on Jun 15,2023 # ** Note: (vsim-3812) Design is being optimized... # ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)". # Loading sv_std.std # Loading work.top_tb(fast) # Loading work.led_if(fast) # Loading work.dip_if(fast) # Loading work.fram_if(fast) # Loading work.clock_if(fast) # Loading work.top(fast) # Loading work.bus(fast) # Loading work.timer(fast) # Loading work.steuerung(fast) # Loading work.spi(fast) # Loading work.FRAM(fast) # Loading work.SPI_Master_With_Single_CS(fast) # Loading work.SPI_Master(fast) # Loading work.parallelport(fast) # Loading work.stimuli(fast) do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl # # create workspace # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # vmap work ./work # Modifying modelsim.ini # # Compile sv-Designfiles # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # -- Compiling interface led_if # -- Compiling interface dip_if # -- Compiling interface fram_if # -- Compiling interface clock_if # # Top level modules: # --none-- # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # -- Compiling module stimuli # # Top level modules: # stimuli # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # -- Compiling module top # -- Compiling interface bus # -- Compiling module parallelport # -- Compiling module steuerung # # Top level modules: # top # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # -- Compiling module top_tb # # Top level modules: # top_tb # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # -- Compiling module timer # # Top level modules: # timer # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # -- Compiling module SPI_Master # # Top level modules: # SPI_Master # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # -- Compiling module SPI_Master_With_Single_CS # # Top level modules: # SPI_Master_With_Single_CS # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # -- Compiling module FRAM # # Top level modules: # FRAM # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:48:17 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # -- Compiling module spi # # Top level modules: # spi # End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # Run Simulation # End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27 # Errors: 3, Warnings: 2 # vsim -cvg63 -voptargs=""+acc"" top_tb # Start time: 14:48:18 on Jun 15,2023 # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # Loading sv_std.std # Loading work.top_tb(fast) # Loading work.led_if(fast) # Loading work.dip_if(fast) # Loading work.fram_if(fast) # Loading work.clock_if(fast) # Loading work.top(fast) # Loading work.bus(fast) # Loading work.timer(fast) # Loading work.steuerung(fast) # Loading work.spi(fast) # Loading work.FRAM(fast) # Loading work.SPI_Master_With_Single_CS(fast) # Loading work.SPI_Master(fast) # Loading work.parallelport(fast) # Loading work.stimuli(fast) add wave -position insertpoint \ sim:/top_tb/t1/fpga_bus/spi_read do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl # # create workspace # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de. # ** Warning: (vlib-34) Library already exists at "work". # QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019 # vmap work ./work # Modifying modelsim.ini # # Compile sv-Designfiles # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv # -- Compiling interface led_if # -- Compiling interface dip_if # -- Compiling interface fram_if # -- Compiling interface clock_if # # Top level modules: # --none-- # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv # -- Compiling module stimuli # # Top level modules: # stimuli # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv # -- Compiling module top # -- Compiling interface bus # -- Compiling module parallelport # -- Compiling module steuerung # # Top level modules: # top # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv # -- Compiling module top_tb # # Top level modules: # top_tb # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv # -- Compiling module timer # # Top level modules: # timer # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv # -- Compiling module SPI_Master # # Top level modules: # SPI_Master # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv # -- Compiling module SPI_Master_With_Single_CS # # Top level modules: # SPI_Master_With_Single_CS # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv # -- Compiling module FRAM # # Top level modules: # FRAM # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019 # Start time: 14:51:02 on Jun 15,2023 # vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv # -- Compiling module spi # # Top level modules: # spi # End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # Run Simulation # End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49 # Errors: 1, Warnings: 2 # vsim -cvg63 -voptargs=""+acc"" top_tb # Start time: 14:51:07 on Jun 15,2023 # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading sv_std.std # Loading work.top_tb(fast) # Loading work.led_if(fast) # Loading work.dip_if(fast) # Loading work.fram_if(fast) # Loading work.clock_if(fast) # Loading work.top(fast) # Loading work.bus(fast) # Loading work.timer(fast) # Loading work.steuerung(fast) # Loading work.spi(fast) # Loading work.FRAM(fast) # Loading work.SPI_Master_With_Single_CS(fast) # Loading work.SPI_Master(fast) # Loading work.parallelport(fast) # Loading work.stimuli(fast) # End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16 # Errors: 3, Warnings: 0