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FRAM_Controller.sv 5.7KB

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  1. module FRAM(
  2. input i_clk, //Module (Module CLock = SPI Clock)
  3. input i_nreset,
  4. input logic [19:0] i_adr, //Memorycell adress in FRAM
  5. input logic [7:0] i_data, //data to write
  6. output logic [7:0] o_data, //data to read
  7. input logic i_rw, //Read = 1, Write = 0
  8. input logic i_status, //If 1 Read Staut register
  9. input logic i_hbn, //If 1 FRAM will enter Hibernation Mode
  10. input logic i_cready, //Starts transmission
  11. output logic o_busy, //Indicates FRAM Busy
  12. // SPI Interface
  13. output o_SPI_Clk,
  14. input i_SPI_MISO,
  15. output o_SPI_MOSI,
  16. output o_SPI_CS_n
  17. );
  18. //FRAM SPI OP Codes
  19. //Write Enable Control
  20. localparam WREN = 8'h06; //Set Write enable latch
  21. localparam WRDI = 8'h04; //Reset write enable latch
  22. //Register Access
  23. localparam RDSR = 8'h05; //Read Status Register
  24. localparam WRSR = 8'h01; //Write Status Register
  25. //Memory Write
  26. localparam WRITE = 8'h02; //Write Memory Data
  27. //Memory Read
  28. localparam READ = 8'h03; //Read Memory Data
  29. localparam FSTRT = 8'h0B; //Fast read memory Data
  30. //Special Sector Memory Access
  31. localparam SSWR = 8'h42; //Spcial Sector Write
  32. localparam SSRD = 8'h4B; //Special Sector Read
  33. //Identification and serial Number
  34. localparam RDID = 8'h9F; //Read Device ID
  35. localparam RUID = 8'h4C; //Read Unique ID
  36. localparam WRSN = 8'hC2; //Write Serial Number
  37. localparam RDSN = 8'hC3; //Read Serial Number
  38. //Low Power Modes
  39. localparam DPD = 8'hBA; // Enter Deep Power-Down
  40. localparam HBN = 8'hB9; // Enter Hibernate Mode
  41. //end FRAM SPI OP Codes
  42. //Controller Specific
  43. logic [3:0] state;
  44. // SPI Specific
  45. parameter SPI_MODE = 0; // CPOL = 0, CPHA = 0
  46. parameter CLKS_PER_HALF_BIT = 2; // 25MHz
  47. parameter MAX_BYTES_PER_CS = 5; // 5 bytes max per chip select cycle
  48. parameter CS_INACTIVE_CLKS = 1; // Adds delay (1clk) between cycles
  49. logic [7:0] r_Master_TX_Byte = 0;
  50. logic r_Master_TX_DV = 1'b0;
  51. logic w_Master_TX_Ready;
  52. logic w_Master_RX_DV;
  53. logic [7:0] w_Master_RX_Byte;
  54. logic [$clog2(MAX_BYTES_PER_CS+1)-1:0] w_Master_RX_Count, r_Master_TX_Count = 3'h1; //Standard 1 Byte pro CS Cycle
  55. SPI_Master_With_Single_CS
  56. #(.SPI_MODE(SPI_MODE), //SPI Mode 0-3
  57. .CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT), //sets Frequency of SPI_CLK
  58. .MAX_BYTES_PER_CS(MAX_BYTES_PER_CS), //Maximum Bytes per CS Cycle
  59. .CS_INACTIVE_CLKS(CS_INACTIVE_CLKS) //Amount of Time holding CS Low befor next command
  60. ) SPI
  61. (
  62. // Control/Data Signals,
  63. .i_Rst_L(i_nreset), // FPGA Reset
  64. .i_Clk(i_clk), // FPGA Clock
  65. // TX (MOSI) Signals
  66. .i_TX_Count(r_Master_TX_Count), // Number of bytes per CS
  67. .i_TX_Byte(r_Master_TX_Byte), // Byte to transmit on MOSI
  68. .i_TX_DV(r_Master_TX_DV), // Data Valid Pulse with i_TX_Byte
  69. .o_TX_Ready(w_Master_TX_Ready), // Transmit Ready for Byte
  70. // RX (MISO) Signals
  71. .o_RX_Count(w_Master_RX_Count), // Index of RX'd byte
  72. .o_RX_DV(w_Master_RX_DV), // Data Valid pulse (1 clock cycle)
  73. .o_RX_Byte(w_Master_RX_Byte), // Byte received on MISO
  74. // SPI Interface
  75. .o_SPI_Clk(o_SPI_Clk),
  76. .i_SPI_MISO(i_SPI_MISO),
  77. .o_SPI_MOSI(o_SPI_MOSI),
  78. .o_SPI_CS_n(o_SPI_CS_n)
  79. );
  80. //end SPI Specific
  81. task SPI_SendByte(input [7:0] data);
  82. @(posedge i_clk);
  83. r_Master_TX_Byte <= data;
  84. r_Master_TX_DV <= 1'b1;
  85. @(posedge i_clk);
  86. r_Master_TX_DV <= 1'b0;
  87. @(posedge i_clk);
  88. @(posedge w_Master_TX_Ready);
  89. endtask //end SPI_SendByte
  90. //FRAM Tasks
  91. task FRAM_Write(input [19:0] adr, input [7:0] data); //vgl. Fig.11
  92. logic [7:0] value;
  93. value <= 8'h0;
  94. //Set Write Enable
  95. r_Master_TX_Count <= 3'b1; //1Byte Transaction
  96. SPI_SendByte(WREN);
  97. //Write to fram
  98. r_Master_TX_Count <= 3'h5; //5 Byte Transaction
  99. SPI_SendByte(WRITE); //OPCode
  100. SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
  101. SPI_SendByte(adr[15:8]); //Adress [15-8]
  102. SPI_SendByte(adr[7:0]); //Adress [7-0]
  103. SPI_SendByte(data); //Data [7:0]
  104. //Reset Write Disable and Verify
  105. do begin
  106. r_Master_TX_Count <= 3'b1; //1Byte Transaction
  107. SPI_SendByte(WRDI); //Set Write Disable
  108. FRAM_Read_Status(value); //Lese Status Register
  109. end while(((value & 8'h2) >> 1) != 0);
  110. endtask //end FRAM_Write
  111. task FRAM_Read(input [19:0] adr, output [7:0] data); //vgl. Fig12
  112. r_Master_TX_Count <= 3'h5; //5 Byte Transaction
  113. SPI_SendByte(READ); //Opcode
  114. SPI_SendByte({4'hF,adr[19:16]}); //Adress [23-16]
  115. SPI_SendByte(adr[15:8]); //Adress [15-8]
  116. SPI_SendByte(adr[7:0]); //Adress [7-0]
  117. SPI_SendByte(8'hAA); //Dummy Bits, read byte in w_Master_RX_Byte
  118. data = w_Master_RX_Byte;
  119. endtask //end FRAM_READ
  120. task FRAM_Read_Status(output [7:0] data); //vgl. Fig9
  121. r_Master_TX_Count <= 3'h2; //2 Byte Transaction
  122. SPI_SendByte(RDSR); //OpCode
  123. SPI_SendByte(8'hFD); //Dummy Bits, read byte in w_Master_RX_Byte
  124. data = w_Master_RX_Byte;
  125. endtask //FRAM_Read_Status
  126. task FRAM_Hibernation(); //vgl. Fig22
  127. r_Master_TX_Count <= 3'h1; //1 Byte Transaction
  128. SPI_SendByte(HBN);
  129. endtask //FRAM_Hibernation
  130. //end FRAM Tasks
  131. always @(posedge i_clk or negedge i_nreset) begin
  132. state[0] = i_cready;
  133. state[1] = i_hbn;
  134. state[2] = i_status;
  135. state[3] = i_rw;
  136. if(~i_nreset) begin //Modul Reset
  137. o_data <= 8'h00;
  138. end //end if
  139. if(w_Master_TX_Ready) begin
  140. case(state) inside
  141. 4'b??11: FRAM_Hibernation();
  142. 4'b?101: FRAM_Read_Status(o_data);
  143. 4'b1001: FRAM_Read(i_adr, o_data);
  144. 4'b0001: FRAM_Write(i_adr, i_data);
  145. default:;
  146. endcase //endcase
  147. end //endif
  148. end //end always
  149. assign o_busy = w_Master_TX_Ready;
  150. endmodule