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interface.sv 1.8KB

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  1. //------------------------------------------------------
  2. //
  3. // File : interface.sv
  4. // Related Files :
  5. // Author(s) : Mueller
  6. // Email : muelleral82290@th-nuernberg.de
  7. // Organization : Georg-Simon-Ohm-Hochschule Nuernberg
  8. // Notes : Stimuli Modul
  9. //
  10. //------------------------------------------------------
  11. // History
  12. //------------------------------------------------------
  13. // Version| Author | Mod. Date | Changes Made:
  14. // v1.00 | Mueller | 11/05/2023 | first code
  15. //------------------------------------------------------
  16. //eoh
  17. //interface for LED
  18. //reg [2:0]rbg stores rgb values that depend on dip[3:2]
  19. interface led_if();
  20. logic [2:0]rgb;
  21. modport led_port_stim(input rgb);
  22. modport led_port_top(output rgb);
  23. endinterface : led_if
  24. //interface for DIPSCHALER
  25. // dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
  26. interface dip_if();
  27. logic [3:0]dip;
  28. modport dip_port_stim(output dip);
  29. modport dip_port_top(input dip);
  30. endinterface : dip_if
  31. //interface for FRAM
  32. // sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
  33. // clk -> system clock / timer
  34. // miso -> testbench output
  35. // mosi -> testbench input
  36. interface fram_if();
  37. logic ss;
  38. logic mosi;
  39. logic miso;
  40. logic sclk;
  41. modport fram_port_stim(input mosi, sclk, ss, output miso);
  42. modport fram_port_top(output mosi, sclk, ss, input miso);
  43. endinterface : fram_if
  44. //testbenchclock replaces the oscillator on the board
  45. interface clock_if();
  46. logic clk;
  47. modport clock_port_stim(output clk);
  48. modport clock_port_top(input clk);
  49. endinterface : clock_if