ESY1_Projekt_2023/uebung_projekt/hdl_src/sv/top_level.sv

// Definition of top level
module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c);
	
	// Initialisation of bus
	bus fpga_bus();
		
	// Initialisation of modules
	timer t(fpga_bus, c);
	steuerung st(fpga_bus, l); 
	spi s(fpga_bus, f);
	parallelport p(fpga_bus, d);
endmodule : top

// Definition of bus interface
interface bus();
	// bus wires
	logic clk; // clock
	logic timer;
	logic [3:0]dip;
	logic [1:0]spi_read;
	
	// modports from modules pov
	modport timer_port(input dip, output timer, clk);			//dip[0]
	modport parallel_port(output dip);							//dip[3:0]
	modport steuerung_port(input dip, timer, spi_read, clk);	//dip[3:0] / spi_read[1:0]
	modport spi_port(input dip, clk, timer, output spi_read);	//spi_read[1:0]
endinterface : bus

// Definition of parallelport
module parallelport(bus.parallel_port b, dip_if.dip_port_top d);
	
	//always at change of the input dip, put the change on the bus
	always@(d.dip[0] or d.dip[1] or d.dip[2] or d.dip[3])
	b.dip = d.dip;	
	
endmodule

module steuerung(bus.steuerung_port b, led_if.led_port_top i);
	/*...
	b.dip[3:0], b.timer, b.spi_read[1:0]
	i.rgb[2:0]
	...*/
endmodule

/*   
_______________________________________________________________________________________________________________
Testbench
					__________________										 		___________________
				   |				  |												|				    |
				   |   DIP-Schalter	  |												|	FRAM-Speicher   |
				   |				  |												|				    |
				   |__________________|												|___________________|
							|																 |
____________________________|________________________________________________________________|_________________
Toplevel					|																 |
							|																 |
				 dip[3:0]-->|																 |<--mosi, miso, sclk, ss
							|												  				 |
					________|_________											     ________|__________
				   |				  |												|				    |
				   |   Parallelport	  |												| SPI-Schnittstelle |
				   |				  |												| & FRAM-Kontroller	|
				   |__________________|												|___________________|
							|																 |
							|																 |
				 dip[3:0]-->|																 |<--dip[3:0], timer, spi_read[1:0]
							|																 |
							|																 |
							---------------------------------------------------------------------BUS
							|																 |
							|																 |
       dip[0], clk, timer-->|																 |<--dip[3:0], timer, spi_read[1:0]
							|																 |
					________|_________			___________________			     	 ________|__________
				   |				  |		   |				   |				|				    |
				   |      Timer		  |		   |  Oszillator-Takt  |				|  Ampel-Steuerung  |
				   |				  |		   |    (auf Board)	   |				|				    |
				   |__________________|		   |___________________|				|___________________|
							|	                         |                                   |
							|							 |									 |
				 	  clk-->------------------------------									 |<--rgb[2:0]
							|																 |
____________________________|________________________________________________________________|___________________
							|																 |
				 	________|_________										 		 ________|__________
				   |				  |												|				    |
				   |       Takt		  |												|	   RGB-LED		|
				   |  (der Testbench) |												|				    |
				   |__________________|												|___________________|


__________________________________________________________________________________________________________________

*/