ESY1_Projekt_2023/uebung_projekt/hdl_src/sv/interface.sv

//------------------------------------------------------
//                                                        
//  File          :  interface.sv
//  Related Files :                                                     
//  Author(s)     :  Mueller                              
//  Email         :  muelleral82290@th-nuernberg.de       
//  Organization  :  Georg-Simon-Ohm-Hochschule Nuernberg 
//  Notes         :  Stimuli Modul 
//
//------------------------------------------------------
//                   History    
//------------------------------------------------------
//    Version| Author   | Mod. Date  | Changes Made:
//    v1.00  | Mueller  | 11/05/2023 | first code
//------------------------------------------------------
//eoh


//interface for LED
//reg [2:0]rbg stores rgb values that depend on dip[3:2]
interface led_if();

	logic [2:0]rgb;
	logic [2:0]rgbn;

	modport led_port_stim(input rgb, rgbn);
	modport led_port_top(output rgb, rgbn);
	

endinterface : led_if

//interface for DIPSCHALER
// dip[3:2] -> select colour, dip[1] -> read ~ 1/write ~ 0, dip[0] -> on ~ 1/off ~ 0
interface dip_if();

	logic [3:0]dip;

	modport dip_port_stim(output dip);
	modport dip_port_top(input dip);

endinterface : dip_if

//interface for FRAM
// sck -> 0 ~ cummonication enabled, 1 ~ communication disabled
// clk -> system clock / timer
// miso -> testbench output
// mosi -> testbench input
interface fram_if();

	logic ss;
	logic mosi;
	logic miso;
	logic sclk;

	modport fram_port_stim(input mosi, sclk, ss, output miso);
	modport fram_port_top(output mosi, sclk, ss, input miso);

endinterface : fram_if

//testbenchclock replaces the oscillator on the board
interface clock_if();

	logic clk;

	modport clock_port_stim(output clk);
	modport clock_port_top(input clk);

endinterface : clock_if