commit 0d1b73e3e01fd095267b81336d9a0160b5de6a5f Author: Johannes Kutning <120175758+JohannesKutning@users.noreply.github.com> Date: Tue Oct 31 07:47:27 2023 +0100 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..67acb7b --- /dev/null +++ b/.gitignore @@ -0,0 +1,20 @@ +.qsys_edit/ +c5_pin_model_dump.txt +db/ +incremental_db/ +*.bak +niosII.sopcinfo +niosII/ +output_files/ +__pycache__/ +*.pyc +.assembler +.fitter +.map +.sta +*.log +*.o +*.oo +*.swp +*.elf + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..e08edb6 --- /dev/null +++ b/Makefile @@ -0,0 +1,199 @@ +# Check for the required nios2-download command +# The command is only available in nios2_command_shell +ifeq (, $(shell which nios2-download)) +$(error "This makefile must be executed within the nios2_command_shell") +endif + +uname = $(shell uname -r) +ifneq (,$(findstring Microsoft,${uname})) +exe_suffix=.exe +endif + +# Programm pathes +quartus_root ?= ${QUARTUS_ROOTDIR} +intel_root ?= $(quartus_root)/.. +sopc_root = $(quartus_root)/sopc_builder + +# Tools +qsys_generate = $(sopc_root)/bin/qsys-generate$(exe_suffix) +niosii_bsp = $(intel_root)/nios2eds/sdk2/bin/nios2-bsp +quartus_map = quartus_map$(exe_suffix) +quartus_fit = quartus_fit$(exe_suffix) +quartus_asm = quartus_asm$(exe_suffix) +quartus_sta = quartus_sta$(exe_suffix) +nios2_bsp_generate_files = nios2-bsp-generate-files$(exe_suffix) +quartus_pgm = quartus_pgm$(exe_suffix) +nios2_download = nios2-download$(exe_suffix) +nios2_terminal = nios2-terminal$(exe_suffix) + +# Directories +niosii_dir = niosII +bsp_dir = software/signal_processing_bsp +app_dir = software/signal_processing +hw_test_dir = tests/hardware +sw_test_dir = tests/software + +# Settings +quartus_project = signal_processing +signal_processing_qsf = signal_processing.qsf + +# Sources +niosii_qsys = niosII.qsys + +# Targets +niosii_qip = $(niosii_dir)/synthesis/niosII.qip +niosii_info = niosII.sopcinfo + +bsp_settings = $(bsp_dir)/settings.bsp +bsp_makefile = $(bsp_dir)/Makefile + +# VHDL source files +hdl_src += \ + hardware/system/sync_ff.vhd \ + hardware/system/sync_rst.vhd \ + hardware/system/pll/pll_main.vhd \ + hardware/system/reg32.vhd \ + hardware/system/avalon_slave_transitions.vhd \ + hardware/system/avalon_slave.vhd \ + hardware/system/data_sink_mux.vhd \ + hardware/system/fifo.vhd \ + hardware/system/data_source_mux.vhd \ + hardware/system/data_channel_control.vhd \ + hardware/system/data_channel.vhd \ + hardware/system/hardware_timestamp.vhd \ + hardware/system/task.vhd \ + hardware/system/float.vhd \ + hardware/system/hardware_task_control.vhd \ + hardware/system/hardware_task.vhd \ + hardware/system/float_add.vhd \ + hardware/signal_processing/add.vhd \ + hardware/system/task_add.vhd \ + hardware/signal_processing/rand.vhd \ + hardware/system/task_rand.vhd \ + hardware/system/cordic_pkg.vhd \ + hardware/system/cordic.vhd \ + hardware/system/fixed_sine.vhd \ + hardware/system/float_sine.vhd \ + hardware/signal_processing/sine.vhd \ + hardware/system/task_sine.vhd \ + hardware/system/Butterfly.v \ + hardware/system/DelayBuffer.v \ + hardware/system/FFT1024_32B.v \ + hardware/system/Multiply.v \ + hardware/system/SdfUnit2.v \ + hardware/system/SdfUnit.v \ + hardware/system/Twiddle1024_32B.v \ + hardware/system/squareRoot_pipe.vhd \ + hardware/system/fft_magnitude_calc.vhd \ + hardware/signal_processing/fft.vhd \ + hardware/system/task_fft.vhd \ + hardware/signal_processing/crc.vhd \ + hardware/system/task_crc.vhd \ + hardware/signal_processing/signal_processing.vhd \ + +# +clean_items += \ + $(niosii_dir) \ + $(niosii_info) \ + .map \ + .fitter \ + .assembler \ + .sta \ + .qsys_edit/ \ + db/ \ + incremental_db/ \ + output_files/ \ + +.PHONY: all \ + niosII \ + fpga \ + program \ + clean \ + app \ + download \ + run \ + tests \ + +all: run + +#------------------------------------------------------------------------------ +# Create the NiosII system from the description file +niosII: $(niosii_info) + +# Create the NiosII sources from the description file +$(niosii_qip): $(niosii_qsys) + @echo Generating the NiosII system from $< ... + @$(qsys_generate) -syn=VHDL $< + +# The NiosII system information file is created in parallel to the .qip file. +$(niosii_info): $(niosii_qip) + +#------------------------------------------------------------------------------ +# Quartus FPGA toolchain contains the mapper, fitter, assembler and static +# timing analysis (sta). +# +fpga: .sta + +# Anaylze and synthesis of the QuartusII project +.map: $(hdl_src) $(niosii_info) $(signal_processing_qsf) + @rm -f $@ + @$(quartus_map) --read_settings_files=on --write_settings_files=off $(quartus_project) -c $(quartus_project) && date > $@ + +# Run the quartus fitter on the project +.fitter: .map $(sdc_src) $(signal_processing_qsf) + @rm -f $@ + @$(quartus_fit) --read_settings_files=on --write_settings_files=off $(quartus_project) -c $(quartus_project) && date > $@ + +.assembler: .fitter + @rm -f $@ + @$(quartus_asm) --read_settings_files=off --write_settings_files=off $(quartus_project) -c $(quartus_project)&& date > $@ + +.sta: .assembler + @rm -f $@ + @$(quartus_sta) $(quartus_project) -c $(quartus_project) && date > $@ + +output_files/signal_processing_time_limited.sof: .sta + +# Create the BSP from the sopc description +bsp: ${bsp_makefile} + +$(bsp_settings): $(niosii_info) + @echo Generating the NiosII BSP from $< ... + @$(niosii_bsp) hal $(bsp_dir) $< + +$(bsp_makefile): $(bsp_settings) + @$(nios2_bsp_generate_files) --settings software/signal_processing_bsp/settings.bsp --bsp-dir software/signal_processing_bsp/ + +app: $(bsp_makefile) + ${MAKE} -C $(app_dir) + +# Programme the FPGA design +program: output_files/signal_processing_time_limited.sof + @$(quartus_pgm) signal_processing.cdf + +# Programme the NiosII software design +download: app + @$(nios2-download) $(app_dir)/signal_processing.elf -g + +# Programme the NiosII software design +run: fpga download + @$(nios2-terminal) + +sw_tests: + @${MAKE} -C tests/software + +hw_tests: + @${MAKE} -C tests/hardware + +device_tests: + @${MAKE} -C tests/device + +tests: sw_tests hw_tests device_tests + +clean: + @rm -rf $(clean_items) + @${MAKE} -C ${hw_test_dir} clean + @${MAKE} -C ${sw_test_dir} clean + @${MAKE} -C ${app_dir} clean + @${MAKE} -C ${bsp_dir} clean + diff --git a/data_channel_hw.tcl b/data_channel_hw.tcl new file mode 100644 index 0000000..d5dfc2c --- /dev/null +++ b/data_channel_hw.tcl @@ -0,0 +1,195 @@ +# TCL File Generated by Component Editor 21.1 +# Fri Sep 09 13:42:23 CEST 2022 +# DO NOT MODIFY + + +# +# data_channel "data_channel" v1.0 +# Johannes Kutning 2022.09.09.13:42:23 +# A data channel for signal data transport +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module data_channel +# +set_module_property DESCRIPTION "A data channel for signal data transport" +set_module_property NAME data_channel +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP signal_processing +set_module_property AUTHOR "Johannes Kutning" +set_module_property DISPLAY_NAME data_channel +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL data_channel +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file data_channel.vhd VHDL PATH hardware/system/data_channel.vhd TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter DEPTH POSITIVE 1024 +set_parameter_property DEPTH DEFAULT_VALUE 1024 +set_parameter_property DEPTH DISPLAY_NAME DEPTH +set_parameter_property DEPTH TYPE POSITIVE +set_parameter_property DEPTH UNITS None +set_parameter_property DEPTH ALLOWED_RANGES 1:2147483647 +set_parameter_property DEPTH HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl maximumPendingWriteTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl ctrl_address address Input 4 +add_interface_port ctrl ctrl_read read Input 1 +add_interface_port ctrl ctrl_readdata readdata Output 32 +add_interface_port ctrl ctrl_write write Input 1 +add_interface_port ctrl ctrl_writedata writedata Input 32 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point hw_sink +# +add_interface hw_sink avalon end +set_interface_property hw_sink addressUnits WORDS +set_interface_property hw_sink associatedClock clock +set_interface_property hw_sink associatedReset reset +set_interface_property hw_sink bitsPerSymbol 8 +set_interface_property hw_sink burstOnBurstBoundariesOnly false +set_interface_property hw_sink burstcountUnits WORDS +set_interface_property hw_sink explicitAddressSpan 0 +set_interface_property hw_sink holdTime 0 +set_interface_property hw_sink linewrapBursts false +set_interface_property hw_sink maximumPendingReadTransactions 0 +set_interface_property hw_sink maximumPendingWriteTransactions 0 +set_interface_property hw_sink readLatency 0 +set_interface_property hw_sink readWaitTime 1 +set_interface_property hw_sink setupTime 0 +set_interface_property hw_sink timingUnits Cycles +set_interface_property hw_sink writeWaitTime 0 +set_interface_property hw_sink ENABLED true +set_interface_property hw_sink EXPORT_OF "" +set_interface_property hw_sink PORT_NAME_MAP "" +set_interface_property hw_sink CMSIS_SVD_VARIABLES "" +set_interface_property hw_sink SVD_ADDRESS_GROUP "" + +add_interface_port hw_sink hw_sink_write write Input 1 +add_interface_port hw_sink hw_sink_writedata writedata Input 32 +set_interface_assignment hw_sink embeddedsw.configuration.isFlash 0 +set_interface_assignment hw_sink embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment hw_sink embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment hw_sink embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point hw_source +# +add_interface hw_source avalon end +set_interface_property hw_source addressUnits WORDS +set_interface_property hw_source associatedClock clock +set_interface_property hw_source associatedReset reset +set_interface_property hw_source bitsPerSymbol 8 +set_interface_property hw_source burstOnBurstBoundariesOnly false +set_interface_property hw_source burstcountUnits WORDS +set_interface_property hw_source explicitAddressSpan 0 +set_interface_property hw_source holdTime 0 +set_interface_property hw_source linewrapBursts false +set_interface_property hw_source maximumPendingReadTransactions 0 +set_interface_property hw_source maximumPendingWriteTransactions 0 +set_interface_property hw_source readLatency 0 +set_interface_property hw_source readWaitTime 1 +set_interface_property hw_source setupTime 0 +set_interface_property hw_source timingUnits Cycles +set_interface_property hw_source writeWaitTime 0 +set_interface_property hw_source ENABLED true +set_interface_property hw_source EXPORT_OF "" +set_interface_property hw_source PORT_NAME_MAP "" +set_interface_property hw_source CMSIS_SVD_VARIABLES "" +set_interface_property hw_source SVD_ADDRESS_GROUP "" + +add_interface_port hw_source hw_source_read read Input 1 +add_interface_port hw_source hw_source_readdata readdata Output 32 +set_interface_assignment hw_source embeddedsw.configuration.isFlash 0 +set_interface_assignment hw_source embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment hw_source embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment hw_source embeddedsw.configuration.isPrintableDevice 0 + diff --git a/hardware/signal_processing.sdc b/hardware/signal_processing.sdc new file mode 100644 index 0000000..f04ccc8 --- /dev/null +++ b/hardware/signal_processing.sdc @@ -0,0 +1,32 @@ +# External clock clk_50 has a frequency of 50 MHz +create_clock -period 20 [get_ports clk_input] + +derive_pll_clocks + +set clk_main u_pll_200|pll_200|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk + +# Input delays for singals in 50 MHz domain +set_input_delay \ + -clock { clk_input } \ + 2 \ + [get_ports {reset_n}] + +# Input delays for singals in 200 MHz domain +set_false_path \ + -from \ + [get_ports {key_start}] + +# Output delays for singals in 200 MHz domain +set_false_path \ + -to \ + [get_ports { \ + leds[0] \ + leds[1] \ + leds[2] \ + leds[3] \ + leds[4] \ + leds[5] \ + leds[6] \ + leds[7] \ + }] + diff --git a/hardware/signal_processing/add.vhd b/hardware/signal_processing/add.vhd new file mode 100644 index 0000000..3e7315a --- /dev/null +++ b/hardware/signal_processing/add.vhd @@ -0,0 +1,77 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.task.all; + +entity add is + port ( + clk : in std_logic; + reset : in std_logic; + + task_start : in std_logic; + task_state : out work.task.State; + + signal_a_read : out std_logic; + signal_a_readdata : in std_logic_vector( 31 downto 0 ); + + signal_b_read : out std_logic; + signal_b_readdata : in std_logic_vector( 31 downto 0 ); + + signal_write : out std_logic; + signal_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity add; + +architecture rtl of add is + signal current_task_state : work.task.State; + signal next_task_state : work.task.State; + signal index : integer range 0 to work.task.STREAM_LEN; + +begin + task_state_transitions : process ( current_task_state, task_start, index ) is + begin + next_task_state <= current_task_state; + case current_task_state is + when work.task.TASK_IDLE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + when work.task.TASK_RUNNING => + if ( index = work.task.STREAM_LEN - 1 ) then + next_task_state <= work.task.TASK_DONE; + end if; + when work.task.TASK_DONE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + end case; + end process task_state_transitions; + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_task_state <= work.task.TASK_IDLE; + index <= 0; + elsif ( rising_edge( clk ) ) then + current_task_state <= next_task_state; + case next_task_state is + when work.task.TASK_IDLE => + index <= 0; + signal_write <= '0'; + when work.task.TASK_RUNNING => + index <= index + 1; + signal_write <= '1'; + signal_writedata <= ( others => '0' ); + when work.task.TASK_DONE => + index <= 0; + signal_write <= '0'; + end case; + end if; + end process sync; + + task_state <= current_task_state; + +end architecture rtl; diff --git a/hardware/signal_processing/crc.vhd b/hardware/signal_processing/crc.vhd new file mode 100644 index 0000000..cf51dcc --- /dev/null +++ b/hardware/signal_processing/crc.vhd @@ -0,0 +1,76 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.task.all; + +entity crc is + port ( + clk : in std_logic; + reset : in std_logic; + + task_start : in std_logic; + task_state : out work.task.State; + + signal_read : out std_logic; + signal_readdata : in std_logic_vector( 31 downto 0 ); + + signal_write : out std_logic; + signal_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity crc; + +architecture rtl of crc is + + signal current_task_state : work.task.State; + signal next_task_state : work.task.State; + signal index : integer range 0 to work.task.STREAM_LEN; + +begin + task_state_transitions : process ( current_task_state, task_start, index ) is + begin + next_task_state <= current_task_state; + case current_task_state is + when work.task.TASK_IDLE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + when work.task.TASK_RUNNING => + if ( index = work.task.STREAM_LEN - 1 ) then + next_task_state <= work.task.TASK_DONE; + end if; + when work.task.TASK_DONE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + end case; + end process task_state_transitions; + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_task_state <= work.task.TASK_IDLE; + index <= 0; + elsif ( rising_edge( clk ) ) then + current_task_state <= next_task_state; + case next_task_state is + when work.task.TASK_IDLE => + index <= 0; + signal_write <= '0'; + when work.task.TASK_RUNNING => + index <= index + 1; + signal_write <= '1'; + signal_writedata <= ( others => '0' ); + when work.task.TASK_DONE => + index <= 0; + signal_write <= '0'; + end case; + end if; + end process sync; + + task_state <= current_task_state; + +end architecture rtl; + diff --git a/hardware/signal_processing/fft.vhd b/hardware/signal_processing/fft.vhd new file mode 100644 index 0000000..a10f221 --- /dev/null +++ b/hardware/signal_processing/fft.vhd @@ -0,0 +1,97 @@ +------------------------------------------------------------------------ +-- fft +-- +-- calculation of FFT magnitude +-- +-- Inputs: +-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO) +-- +-- Outputs +-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO) +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.task.all; + use work.float.all; + +entity fft is + generic ( + + -- input data width of real/img part + input_data_width : integer := 32; + + -- output data width of real/img part + output_data_width : integer := 32 + + ); + port ( + clk : in std_logic; + reset : in std_logic; + + task_start : in std_logic; + task_state : out work.task.State; + + signal_read : out std_logic; + signal_readdata : in std_logic_vector( 31 downto 0 ); + + signal_write : out std_logic; + signal_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity fft; + +architecture rtl of fft is + + signal current_task_state : work.task.State; + signal next_task_state : work.task.State; + signal index : integer range 0 to work.task.STREAM_LEN; + +begin + task_state_transitions : process ( current_task_state, task_start, index ) is + begin + next_task_state <= current_task_state; + case current_task_state is + when work.task.TASK_IDLE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + when work.task.TASK_RUNNING => + if ( index = work.task.STREAM_LEN - 1 ) then + next_task_state <= work.task.TASK_DONE; + end if; + when work.task.TASK_DONE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + end case; + end process task_state_transitions; + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_task_state <= work.task.TASK_IDLE; + index <= 0; + elsif ( rising_edge( clk ) ) then + current_task_state <= next_task_state; + case next_task_state is + when work.task.TASK_IDLE => + index <= 0; + signal_write <= '0'; + when work.task.TASK_RUNNING => + index <= index + 1; + signal_write <= '1'; + signal_writedata <= ( others => '0' ); + when work.task.TASK_DONE => + index <= 0; + signal_write <= '0'; + end case; + end if; + end process sync; + + task_state <= current_task_state; + +end architecture rtl; diff --git a/hardware/signal_processing/rand.vhd b/hardware/signal_processing/rand.vhd new file mode 100644 index 0000000..3a229f3 --- /dev/null +++ b/hardware/signal_processing/rand.vhd @@ -0,0 +1,73 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.task.all; + +entity rand is + port ( + clk : in std_logic; + reset : in std_logic; + + task_start : in std_logic; + task_state : out work.task.State; + seed : in work.reg32.word; + + signal_write : out std_logic; + signal_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity rand; + +architecture rtl of rand is + + signal current_task_state : work.task.State; + signal next_task_state : work.task.State; + signal index : integer range 0 to work.task.STREAM_LEN; + +begin + task_state_transitions : process ( current_task_state, task_start, index ) is + begin + next_task_state <= current_task_state; + case current_task_state is + when work.task.TASK_IDLE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + when work.task.TASK_RUNNING => + if ( index = work.task.STREAM_LEN - 1 ) then + next_task_state <= work.task.TASK_DONE; + end if; + when work.task.TASK_DONE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + end case; + end process task_state_transitions; + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_task_state <= work.task.TASK_IDLE; + index <= 0; + elsif ( rising_edge( clk ) ) then + current_task_state <= next_task_state; + case next_task_state is + when work.task.TASK_IDLE => + index <= 0; + signal_write <= '0'; + when work.task.TASK_RUNNING => + index <= index + 1; + signal_write <= '1'; + signal_writedata <= ( others => '0' ); + when work.task.TASK_DONE => + index <= 0; + signal_write <= '0'; + end case; + end if; + end process sync; + + task_state <= current_task_state; + +end architecture rtl; diff --git a/hardware/signal_processing/signal_processing.vhd b/hardware/signal_processing/signal_processing.vhd new file mode 100644 index 0000000..f2e491f --- /dev/null +++ b/hardware/signal_processing/signal_processing.vhd @@ -0,0 +1,363 @@ +--! Use ieee library for std_logic types. +library ieee; + use ieee.std_logic_1164.all; + +--! Use the niosII library for all processor system components +library niosII; + +--! Use the pll_200 library for the PLL 200 MHz clock generation +library pll_main; + +entity signal_processing is + port + ( + clk_input : in std_logic; + reset_n : in std_logic; + + --! Push button key_0 used to start a single execution of the signal + --! processing. + key_start : in std_logic; + + leds : out std_logic_vector( 7 downto 0 ) + ); +end entity signal_processing; + +architecture struct of signal_processing is + + --! input clock synchronous reset + signal sync_reset : std_logic; + + --! main clock for the NiosII system + signal clk_main : std_logic; + --! main clock from PLL is locked and the system reset can be released. + signal locked_main : std_logic; + --! main clock synchronous reset + signal sync_reset_main : std_logic; + signal sync_reset_main_n : std_logic; + + signal sw_leds : std_logic_vector( 7 downto 0 ); + signal hw_leds : std_logic_vector( 7 downto 0 ); + + signal hardware_task_0_address : std_logic_vector(3 downto 0); + signal hardware_task_0_read : std_logic; + signal hardware_task_0_readdata : std_logic_vector(31 downto 0); + signal hardware_task_0_write : std_logic; + signal hardware_task_0_writedata : std_logic_vector(31 downto 0); + + signal hardware_task_1_address : std_logic_vector(3 downto 0); + signal hardware_task_1_read : std_logic; + signal hardware_task_1_readdata : std_logic_vector(31 downto 0); + signal hardware_task_1_write : std_logic; + signal hardware_task_1_writedata : std_logic_vector(31 downto 0); + + signal hardware_task_2_address : std_logic_vector(3 downto 0); + signal hardware_task_2_read : std_logic; + signal hardware_task_2_readdata : std_logic_vector(31 downto 0); + signal hardware_task_2_write : std_logic; + signal hardware_task_2_writedata : std_logic_vector(31 downto 0); + + signal hardware_task_3_address : std_logic_vector(3 downto 0); + signal hardware_task_3_read : std_logic; + signal hardware_task_3_readdata : std_logic_vector(31 downto 0); + signal hardware_task_3_write : std_logic; + signal hardware_task_3_writedata : std_logic_vector(31 downto 0); + + signal hardware_task_4_address : std_logic_vector(3 downto 0); + signal hardware_task_4_read : std_logic; + signal hardware_task_4_readdata : std_logic_vector(31 downto 0); + signal hardware_task_4_write : std_logic; + signal hardware_task_4_writedata : std_logic_vector(31 downto 0); + + signal hardware_task_5_address : std_logic_vector(3 downto 0); + signal hardware_task_5_read : std_logic; + signal hardware_task_5_readdata : std_logic_vector(31 downto 0); + signal hardware_task_5_write : std_logic; + signal hardware_task_5_writedata : std_logic_vector(31 downto 0); + + signal hardware_task_6_address : std_logic_vector(3 downto 0); + signal hardware_task_6_read : std_logic; + signal hardware_task_6_readdata : std_logic_vector(31 downto 0); + signal hardware_task_6_write : std_logic; + signal hardware_task_6_writedata : std_logic_vector(31 downto 0); + + signal data_channel_0_hw_sink_write : std_logic; + signal data_channel_0_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_0_hw_source_read : std_logic; + signal data_channel_0_hw_source_readdata : std_logic_vector(31 downto 0); + + signal data_channel_1_hw_sink_write : std_logic; + signal data_channel_1_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_1_hw_source_read : std_logic; + signal data_channel_1_hw_source_readdata : std_logic_vector(31 downto 0); + + signal data_channel_2_hw_sink_write : std_logic; + signal data_channel_2_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_2_hw_source_read : std_logic; + signal data_channel_2_hw_source_readdata : std_logic_vector(31 downto 0); + + signal data_channel_3_hw_sink_write : std_logic; + signal data_channel_3_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_3_hw_source_read : std_logic; + signal data_channel_3_hw_source_readdata : std_logic_vector(31 downto 0); + + signal data_channel_4_hw_sink_write : std_logic; + signal data_channel_4_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_4_hw_source_read : std_logic; + signal data_channel_4_hw_source_readdata : std_logic_vector(31 downto 0); + + signal data_channel_5_hw_sink_write : std_logic; + signal data_channel_5_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_5_hw_source_read : std_logic; + signal data_channel_5_hw_source_readdata : std_logic_vector(31 downto 0); + + signal data_channel_6_hw_sink_write : std_logic; + signal data_channel_6_hw_sink_writedata : std_logic_vector(31 downto 0); + signal data_channel_6_hw_source_read : std_logic; + signal data_channel_6_hw_source_readdata : std_logic_vector(31 downto 0); +begin + + -- Synchronize the external reset to the external clock domain + u_sync_rst_50: entity work.sync_rst + port map + ( + clk => clk_input, + reset => not reset_n, + rst_sync => sync_reset + ); + + -- PLL for the main system clock + u_pll_main: entity pll_main.pll_main + port map + ( + refclk => clk_input, -- in std_logic + rst => sync_reset, -- in std_logic + outclk_0 => clk_main, -- out std_logic + locked => locked_main -- out std_logic + ); + + -- Synchronize the main reset to the main clock domain + u_sync_rst_main: entity work.sync_rst + port map + ( + clk => clk_main, + reset => not locked_main and sync_reset, + rst_sync => sync_reset_main + ); + sync_reset_main_n <= not sync_reset_main; + + -- NiosII system + u_niosII : entity niosii.niosII + port map + ( + clk_clk => clk_main, + reset_reset_n => sync_reset_main_n, + + key_start_export => key_start, + leds_export => sw_leds, + + data_channel_0_hw_sink_write => data_channel_0_hw_sink_write, + data_channel_0_hw_sink_writedata => data_channel_0_hw_sink_writedata, + data_channel_0_hw_source_read => data_channel_0_hw_source_read, + data_channel_0_hw_source_readdata => data_channel_0_hw_source_readdata, + + data_channel_1_hw_sink_write => data_channel_1_hw_sink_write, + data_channel_1_hw_sink_writedata => data_channel_1_hw_sink_writedata, + data_channel_1_hw_source_read => data_channel_1_hw_source_read, + data_channel_1_hw_source_readdata => data_channel_1_hw_source_readdata, + + data_channel_2_hw_sink_write => data_channel_2_hw_sink_write, + data_channel_2_hw_sink_writedata => data_channel_2_hw_sink_writedata, + data_channel_2_hw_source_read => data_channel_2_hw_source_read, + data_channel_2_hw_source_readdata => data_channel_2_hw_source_readdata, + + data_channel_3_hw_sink_write => data_channel_3_hw_sink_write, + data_channel_3_hw_sink_writedata => data_channel_3_hw_sink_writedata, + data_channel_3_hw_source_read => data_channel_3_hw_source_read, + data_channel_3_hw_source_readdata => data_channel_3_hw_source_readdata, + + data_channel_4_hw_sink_write => data_channel_4_hw_sink_write, + data_channel_4_hw_sink_writedata => data_channel_4_hw_sink_writedata, + data_channel_4_hw_source_read => data_channel_4_hw_source_read, + data_channel_4_hw_source_readdata => data_channel_4_hw_source_readdata, + + data_channel_5_hw_sink_write => data_channel_5_hw_sink_write, + data_channel_5_hw_sink_writedata => data_channel_5_hw_sink_writedata, + data_channel_5_hw_source_read => data_channel_5_hw_source_read, + data_channel_5_hw_source_readdata => data_channel_5_hw_source_readdata, + + data_channel_6_hw_sink_write => data_channel_6_hw_sink_write, + data_channel_6_hw_sink_writedata => data_channel_6_hw_sink_writedata, + data_channel_6_hw_source_read => data_channel_6_hw_source_read, + data_channel_6_hw_source_readdata => data_channel_6_hw_source_readdata, + + hardware_task_0_task_address => hardware_task_0_address, + hardware_task_0_task_read => hardware_task_0_read, + hardware_task_0_task_readdata => hardware_task_0_readdata, + hardware_task_0_task_write => hardware_task_0_write, + hardware_task_0_task_writedata => hardware_task_0_writedata, + + hardware_task_1_task_address => hardware_task_1_address, + hardware_task_1_task_read => hardware_task_1_read, + hardware_task_1_task_readdata => hardware_task_1_readdata, + hardware_task_1_task_write => hardware_task_1_write, + hardware_task_1_task_writedata => hardware_task_1_writedata, + + hardware_task_2_task_address => hardware_task_2_address, + hardware_task_2_task_read => hardware_task_2_read, + hardware_task_2_task_readdata => hardware_task_2_readdata, + hardware_task_2_task_write => hardware_task_2_write, + hardware_task_2_task_writedata => hardware_task_2_writedata, + + hardware_task_3_task_address => hardware_task_3_address, + hardware_task_3_task_read => hardware_task_3_read, + hardware_task_3_task_readdata => hardware_task_3_readdata, + hardware_task_3_task_write => hardware_task_3_write, + hardware_task_3_task_writedata => hardware_task_3_writedata, + + hardware_task_4_task_address => hardware_task_4_address, + hardware_task_4_task_read => hardware_task_4_read, + hardware_task_4_task_readdata => hardware_task_4_readdata, + hardware_task_4_task_write => hardware_task_4_write, + hardware_task_4_task_writedata => hardware_task_4_writedata, + + hardware_task_5_task_address => hardware_task_5_address, + hardware_task_5_task_read => hardware_task_5_read, + hardware_task_5_task_readdata => hardware_task_5_readdata, + hardware_task_5_task_write => hardware_task_5_write, + hardware_task_5_task_writedata => hardware_task_5_writedata, + + hardware_task_6_task_address => hardware_task_6_address, + hardware_task_6_task_read => hardware_task_6_read, + hardware_task_6_task_readdata => hardware_task_6_readdata, + hardware_task_6_task_write => hardware_task_6_write, + hardware_task_6_task_writedata => hardware_task_6_writedata + ); + + u_task_sine: entity work.task_sine + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_0_address, + read => hardware_task_0_read, + readdata => hardware_task_0_readdata, + write => hardware_task_0_write, + writedata => hardware_task_0_writedata, + + signal_write => data_channel_0_hw_sink_write , + signal_writedata => data_channel_0_hw_sink_writedata + ); + + u_task_cosine: entity work.task_sine + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_1_address, + read => hardware_task_1_read, + readdata => hardware_task_1_readdata, + write => hardware_task_1_write, + writedata => hardware_task_1_writedata, + + signal_write => data_channel_1_hw_sink_write , + signal_writedata => data_channel_1_hw_sink_writedata + ); + + u_task_rand: entity work.task_rand + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_2_address, + read => hardware_task_2_read, + readdata => hardware_task_2_readdata, + write => hardware_task_2_write, + writedata => hardware_task_2_writedata, + + signal_write => data_channel_2_hw_sink_write , + signal_writedata => data_channel_2_hw_sink_writedata + ); + + u_task_add_sine_cosine: entity work.task_add + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_3_address, + read => hardware_task_3_read, + readdata => hardware_task_3_readdata, + write => hardware_task_3_write, + writedata => hardware_task_3_writedata, + + signal_a_read => data_channel_0_hw_source_read, + signal_a_readdata => data_channel_0_hw_source_readdata, + + signal_b_read => data_channel_1_hw_source_read, + signal_b_readdata => data_channel_1_hw_source_readdata, + + signal_write => data_channel_3_hw_sink_write , + signal_writedata => data_channel_3_hw_sink_writedata + ); + + u_task_add_rand: entity work.task_add + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_4_address, + read => hardware_task_4_read, + readdata => hardware_task_4_readdata, + write => hardware_task_4_write, + writedata => hardware_task_4_writedata, + + signal_a_read => data_channel_2_hw_source_read, + signal_a_readdata => data_channel_2_hw_source_readdata, + + signal_b_read => data_channel_3_hw_source_read, + signal_b_readdata => data_channel_3_hw_source_readdata, + + signal_write => data_channel_4_hw_sink_write , + signal_writedata => data_channel_4_hw_sink_writedata + ); + + u_task_fft: entity work.task_fft + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_5_address, + read => hardware_task_5_read, + readdata => hardware_task_5_readdata, + write => hardware_task_5_write, + writedata => hardware_task_5_writedata, + + signal_read => data_channel_4_hw_source_read, + signal_readdata => data_channel_4_hw_source_readdata, + + signal_write => data_channel_5_hw_sink_write , + signal_writedata => data_channel_5_hw_sink_writedata + ); + + u_task_crc: entity work.task_crc + port map ( + clk => clk_main, + reset => sync_reset_main, + + address => hardware_task_6_address, + read => hardware_task_6_read, + readdata => hardware_task_6_readdata, + write => hardware_task_6_write, + writedata => hardware_task_6_writedata, + + signal_read => data_channel_5_hw_source_read, + signal_readdata => data_channel_5_hw_source_readdata, + + signal_write => data_channel_6_hw_sink_write , + signal_writedata => data_channel_6_hw_sink_writedata + ); + + hw_leds <= ( 0 => reset_n, 1 => sync_reset, 2 => locked_main, 3 => sync_reset_main, others => '0' ); + leds <= sw_leds or hw_leds; + +end architecture struct; + diff --git a/hardware/signal_processing/sine.vhd b/hardware/signal_processing/sine.vhd new file mode 100644 index 0000000..36fb916 --- /dev/null +++ b/hardware/signal_processing/sine.vhd @@ -0,0 +1,77 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.float.all; + use work.task.all; + +entity sine is + port ( + clk : in std_logic; + reset : in std_logic; + + task_start : in std_logic; + task_state : out work.task.State; + + step_size : in work.reg32.word; + phase : in work.reg32.word; + amplitude : in work.reg32.word; + + signal_write : out std_logic; + signal_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity sine; + +architecture rtl of sine is + + signal current_task_state : work.task.State; + signal next_task_state : work.task.State; + signal index : integer range 0 to work.task.STREAM_LEN; + +begin + task_state_transitions : process ( current_task_state, task_start, index ) is + begin + next_task_state <= current_task_state; + case current_task_state is + when work.task.TASK_IDLE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + when work.task.TASK_RUNNING => + if ( index = work.task.STREAM_LEN - 1 ) then + next_task_state <= work.task.TASK_DONE; + end if; + when work.task.TASK_DONE => + if ( task_start = '1' ) then + next_task_state <= work.task.TASK_RUNNING; + end if; + end case; + end process task_state_transitions; + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_task_state <= work.task.TASK_IDLE; + index <= 0; + elsif ( rising_edge( clk ) ) then + current_task_state <= next_task_state; + case next_task_state is + when work.task.TASK_IDLE => + index <= 0; + signal_write <= '0'; + when work.task.TASK_RUNNING => + index <= index + 1; + signal_write <= '1'; + signal_writedata <= ( others => '0' ); + when work.task.TASK_DONE => + index <= 0; + signal_write <= '0'; + end case; + end if; + end process sync; + + task_state <= current_task_state; + +end architecture rtl; diff --git a/hardware/system/Butterfly.v b/hardware/system/Butterfly.v new file mode 100644 index 0000000..61df798 --- /dev/null +++ b/hardware/system/Butterfly.v @@ -0,0 +1,32 @@ +//---------------------------------------------------------------------- +// Butterfly: Add/Sub and Scaling +//---------------------------------------------------------------------- +module Butterfly #( + parameter WIDTH = 16, + parameter RH = 0 // Round Half Up +)( + input signed [WIDTH-1:0] x0_re, // Input Data #0 (Real) + input signed [WIDTH-1:0] x0_im, // Input Data #0 (Imag) + input signed [WIDTH-1:0] x1_re, // Input Data #1 (Real) + input signed [WIDTH-1:0] x1_im, // Input Data #1 (Imag) + output signed [WIDTH-1:0] y0_re, // Output Data #0 (Real) + output signed [WIDTH-1:0] y0_im, // Output Data #0 (Imag) + output signed [WIDTH-1:0] y1_re, // Output Data #1 (Real) + output signed [WIDTH-1:0] y1_im // Output Data #1 (Imag) +); + +wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im; + +// Add/Sub +assign add_re = x0_re + x1_re; +assign add_im = x0_im + x1_im; +assign sub_re = x0_re - x1_re; +assign sub_im = x0_im - x1_im; + +// Scaling +assign y0_re = (add_re + RH) >>> 1; +assign y0_im = (add_im + RH) >>> 1; +assign y1_re = (sub_re + RH) >>> 1; +assign y1_im = (sub_im + RH) >>> 1; + +endmodule diff --git a/hardware/system/DelayBuffer.v b/hardware/system/DelayBuffer.v new file mode 100644 index 0000000..19bff72 --- /dev/null +++ b/hardware/system/DelayBuffer.v @@ -0,0 +1,32 @@ +//---------------------------------------------------------------------- +// DelayBuffer: Generate Constant Delay +//---------------------------------------------------------------------- +module DelayBuffer #( + parameter DEPTH = 32, + parameter WIDTH = 16 +)( + input clock, // Master Clock + input [WIDTH-1:0] di_re, // Data Input (Real) + input [WIDTH-1:0] di_im, // Data Input (Imag) + output [WIDTH-1:0] do_re, // Data Output (Real) + output [WIDTH-1:0] do_im // Data Output (Imag) +); + +reg [WIDTH-1:0] buf_re[0:DEPTH-1]; +reg [WIDTH-1:0] buf_im[0:DEPTH-1]; +integer n; + +// Shift Buffer +always @(posedge clock) begin + for (n = DEPTH-1; n > 0; n = n - 1) begin + buf_re[n] <= buf_re[n-1]; + buf_im[n] <= buf_im[n-1]; + end + buf_re[0] <= di_re; + buf_im[0] <= di_im; +end + +assign do_re = buf_re[DEPTH-1]; +assign do_im = buf_im[DEPTH-1]; + +endmodule diff --git a/hardware/system/FFT1024_32B.v b/hardware/system/FFT1024_32B.v new file mode 100644 index 0000000..f426d98 --- /dev/null +++ b/hardware/system/FFT1024_32B.v @@ -0,0 +1,89 @@ +//---------------------------------------------------------------------- +// FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback +//---------------------------------------------------------------------- +module FFTMAIN #( + parameter WIDTH = 32 +)( + input clock, // Master Clock + input reset, // Active High Asynchronous Reset + input di_en, // Input Data Enable + input [WIDTH-1:0] di_re, // Input Data (Real) + input [WIDTH-1:0] di_im, // Input Data (Imag) + output do_en, // Output Data Enable + output [WIDTH-1:0] do_re, // Output Data (Real) + output [WIDTH-1:0] do_im // Output Data (Imag) +); +//---------------------------------------------------------------------- +// Data must be input consecutively in natural order. +// The result is scaled to 1/N and output in bit-reversed order. +//---------------------------------------------------------------------- + +wire su1_do_en; +wire[WIDTH-1:0] su1_do_re; +wire[WIDTH-1:0] su1_do_im; +wire su2_do_en; +wire[WIDTH-1:0] su2_do_re; +wire[WIDTH-1:0] su2_do_im; +wire su3_do_en; +wire[WIDTH-1:0] su3_do_re; +wire[WIDTH-1:0] su3_do_im; +wire su4_do_en; +wire[WIDTH-1:0] su4_do_re; +wire[WIDTH-1:0] su4_do_im; + +SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (di_en ), // i + .di_re (di_re ), // i + .di_im (di_im ), // i + .do_en (su1_do_en ), // o + .do_re (su1_do_re ), // o + .do_im (su1_do_im ) // o +); + +SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su1_do_en ), // i + .di_re (su1_do_re ), // i + .di_im (su1_do_im ), // i + .do_en (su2_do_en ), // o + .do_re (su2_do_re ), // o + .do_im (su2_do_im ) // o +); + +SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su2_do_en ), // i + .di_re (su2_do_re ), // i + .di_im (su2_do_im ), // i + .do_en (su3_do_en ), // o + .do_re (su3_do_re ), // o + .do_im (su3_do_im ) // o +); + +SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su3_do_en ), // i + .di_re (su3_do_re ), // i + .di_im (su3_do_im ), // i + .do_en (su4_do_en ), // o + .do_re (su4_do_re ), // o + .do_im (su4_do_im ) // o +); + +SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 ( + .clock (clock ), // i + .reset (reset ), // i + .di_en (su4_do_en ), // i + .di_re (su4_do_re ), // i + .di_im (su4_do_im ), // i + .do_en (do_en ), // o + .do_re (do_re ), // o + .do_im (do_im ) // o +); + +endmodule diff --git a/hardware/system/Multiply.v b/hardware/system/Multiply.v new file mode 100644 index 0000000..6172571 --- /dev/null +++ b/hardware/system/Multiply.v @@ -0,0 +1,35 @@ +//---------------------------------------------------------------------- +// Multiply: Complex Multiplier +//---------------------------------------------------------------------- +module Multiply #( + parameter WIDTH = 16 +)( + input signed [WIDTH-1:0] a_re, + input signed [WIDTH-1:0] a_im, + input signed [WIDTH-1:0] b_re, + input signed [WIDTH-1:0] b_im, + output signed [WIDTH-1:0] m_re, + output signed [WIDTH-1:0] m_im +); + +wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi; +wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi; + +// Signed Multiplication +assign arbr = a_re * b_re; +assign arbi = a_re * b_im; +assign aibr = a_im * b_re; +assign aibi = a_im * b_im; + +// Scaling +assign sc_arbr = arbr >>> (WIDTH-1); +assign sc_arbi = arbi >>> (WIDTH-1); +assign sc_aibr = aibr >>> (WIDTH-1); +assign sc_aibi = aibi >>> (WIDTH-1); + +// Sub/Add +// These sub/add may overflow if unnormalized data is input. +assign m_re = sc_arbr - sc_aibi; +assign m_im = sc_arbi + sc_aibr; + +endmodule diff --git a/hardware/system/SdfUnit.v b/hardware/system/SdfUnit.v new file mode 100644 index 0000000..67edc49 --- /dev/null +++ b/hardware/system/SdfUnit.v @@ -0,0 +1,277 @@ +//---------------------------------------------------------------------- +// SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT +//---------------------------------------------------------------------- +module SdfUnit #( + parameter N = 64, // Number of FFT Point + parameter M = 64, // Twiddle Resolution + parameter WIDTH = 16 // Data Bit Length +)( + input clock, // Master Clock + input reset, // Active High Asynchronous Reset + input di_en, // Input Data Enable + input [WIDTH-1:0] di_re, // Input Data (Real) + input [WIDTH-1:0] di_im, // Input Data (Imag) + output do_en, // Output Data Enable + output [WIDTH-1:0] do_re, // Output Data (Real) + output [WIDTH-1:0] do_im // Output Data (Imag) +); + +// log2 constant function +function integer log2; + input integer x; + integer value; + begin + value = x-1; + for (log2=0; value>0; log2=log2+1) + value = value>>1; + end +endfunction + +localparam LOG_N = log2(N); // Bit Length of N +localparam LOG_M = log2(M); // Bit Length of M + +//---------------------------------------------------------------------- +// Internal Regs and Nets +//---------------------------------------------------------------------- +// 1st Butterfly +reg [LOG_N-1:0] di_count; // Input Data Count +wire bf1_bf; // Butterfly Add/Sub Enable +wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real) +wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag) +wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real) +wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag) +wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real) +wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag) +wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real) +wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag) +wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real) +wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag) +wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real) +wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag) +wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real) +wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag) +reg bf1_sp_en; // Single-Path Data Enable +reg [LOG_N-1:0] bf1_count; // Single-Path Data Count +wire bf1_start; // Single-Path Output Trigger +wire bf1_end; // End of Single-Path Data +wire bf1_mj; // Twiddle (-j) Enable +reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real) +reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag) + +// 2nd Butterfly +reg bf2_bf; // Butterfly Add/Sub Enable +wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real) +wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag) +wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real) +wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag) +wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real) +wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag) +wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real) +wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag) +wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real) +wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag) +wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real) +wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag) +wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real) +wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag) +reg bf2_sp_en; // Single-Path Data Enable +reg [LOG_N-1:0] bf2_count; // Single-Path Data Count +reg bf2_start; // Single-Path Output Trigger +wire bf2_end; // End of Single-Path Data +reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real) +reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag) +reg bf2_do_en; // 2nd Butterfly Output Data Enable + +// Multiplication +wire[1:0] tw_sel; // Twiddle Select (2n/n/3n) +wire[LOG_N-3:0] tw_num; // Twiddle Number (n) +wire[LOG_N-1:0] tw_addr; // Twiddle Table Address +wire[WIDTH-1:0] tw_re; // Twiddle Factor (Real) +wire[WIDTH-1:0] tw_im; // Twiddle Factor (Imag) +reg mu_en; // Multiplication Enable +wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real) +wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag) +wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real) +wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag) +reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real) +reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag) +reg mu_do_en; // Multiplication Output Data Enable + +//---------------------------------------------------------------------- +// 1st Butterfly +//---------------------------------------------------------------------- +always @(posedge clock or posedge reset) begin + if (reset) begin + di_count <= {LOG_N{1'b0}}; + end else begin + di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}}; + end +end +assign bf1_bf = di_count[LOG_M-1]; + +// Set unknown value x for verification +assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}}; +assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}}; +assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}}; +assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}}; + +Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 ( + .x0_re (bf1_x0_re ), // i + .x0_im (bf1_x0_im ), // i + .x1_re (bf1_x1_re ), // i + .x1_im (bf1_x1_im ), // i + .y0_re (bf1_y0_re ), // o + .y0_im (bf1_y0_im ), // o + .y1_re (bf1_y1_re ), // o + .y1_im (bf1_y1_im ) // o +); + +DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 ( + .clock (clock ), // i + .di_re (db1_di_re ), // i + .di_im (db1_di_im ), // i + .do_re (db1_do_re ), // o + .do_im (db1_do_im ) // o +); + +assign db1_di_re = bf1_bf ? bf1_y1_re : di_re; +assign db1_di_im = bf1_bf ? bf1_y1_im : di_im; +assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re; +assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im; + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf1_sp_en <= 1'b0; + bf1_count <= {LOG_N{1'b0}}; + end else begin + bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en; + bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}}; + end +end +assign bf1_start = (di_count == (2**(LOG_M-1)-1)); +assign bf1_end = (bf1_count == (2**LOG_N-1)); +assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3); + +always @(posedge clock) begin + bf1_do_re <= bf1_sp_re; + bf1_do_im <= bf1_sp_im; +end + +//---------------------------------------------------------------------- +// 2nd Butterfly +//---------------------------------------------------------------------- +always @(posedge clock) begin + bf2_bf <= bf1_count[LOG_M-2]; +end + +// Set unknown value x for verification +assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}}; +assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}}; +assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}}; +assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}}; + +// Negative bias occurs when RH=0 and positive bias occurs when RH=1. +// Using both alternately reduces the overall rounding error. +Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 ( + .x0_re (bf2_x0_re ), // i + .x0_im (bf2_x0_im ), // i + .x1_re (bf2_x1_re ), // i + .x1_im (bf2_x1_im ), // i + .y0_re (bf2_y0_re ), // o + .y0_im (bf2_y0_im ), // o + .y1_re (bf2_y1_re ), // o + .y1_im (bf2_y1_im ) // o +); + +DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 ( + .clock (clock ), // i + .di_re (db2_di_re ), // i + .di_im (db2_di_im ), // i + .do_re (db2_do_re ), // o + .do_im (db2_do_im ) // o +); + +assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re; +assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im; +assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re; +assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im; + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf2_sp_en <= 1'b0; + bf2_count <= {LOG_N{1'b0}}; + end else begin + bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en; + bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}}; + end +end + +always @(posedge clock) begin + bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en; +end +assign bf2_end = (bf2_count == (2**LOG_N-1)); + +always @(posedge clock) begin + bf2_do_re <= bf2_sp_re; + bf2_do_im <= bf2_sp_im; +end + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf2_do_en <= 1'b0; + end else begin + bf2_do_en <= bf2_sp_en; + end +end + +//---------------------------------------------------------------------- +// Multiplication +//---------------------------------------------------------------------- +assign tw_sel[1] = bf2_count[LOG_M-2]; +assign tw_sel[0] = bf2_count[LOG_M-1]; +assign tw_num = bf2_count << (LOG_N-LOG_M); +assign tw_addr = tw_num * tw_sel; + +Twiddle TW ( + .clock (clock ), // i + .addr (tw_addr), // i + .tw_re (tw_re ), // o + .tw_im (tw_im ) // o +); + +// Multiplication is bypassed when twiddle address is 0. +always @(posedge clock) begin + mu_en <= (tw_addr != {LOG_N{1'b0}}); +end +// Set unknown value x for verification +assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}}; +assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}}; + +Multiply #(.WIDTH(WIDTH)) MU ( + .a_re (mu_a_re), // i + .a_im (mu_a_im), // i + .b_re (tw_re ), // i + .b_im (tw_im ), // i + .m_re (mu_m_re), // o + .m_im (mu_m_im) // o +); + +always @(posedge clock) begin + mu_do_re <= mu_en ? mu_m_re : bf2_do_re; + mu_do_im <= mu_en ? mu_m_im : bf2_do_im; +end + +always @(posedge clock or posedge reset) begin + if (reset) begin + mu_do_en <= 1'b0; + end else begin + mu_do_en <= bf2_do_en; + end +end + +// No multiplication required at final stage +assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en; +assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re; +assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im; + +endmodule diff --git a/hardware/system/SdfUnit2.v b/hardware/system/SdfUnit2.v new file mode 100644 index 0000000..13bcf5a --- /dev/null +++ b/hardware/system/SdfUnit2.v @@ -0,0 +1,94 @@ +//---------------------------------------------------------------------- +// SdfUnit2: Radix-2 SDF Dedicated for Twiddle Resolution M = 2 +//---------------------------------------------------------------------- +module SdfUnit2 #( + parameter WIDTH = 16, // Data Bit Length + parameter BF_RH = 0 // Butterfly Round Half Up +)( + input clock, // Master Clock + input reset, // Active High Asynchronous Reset + input di_en, // Input Data Enable + input [WIDTH-1:0] di_re, // Input Data (Real) + input [WIDTH-1:0] di_im, // Input Data (Imag) + output reg do_en, // Output Data Enable + output reg [WIDTH-1:0] do_re, // Output Data (Real) + output reg [WIDTH-1:0] do_im // Output Data (Imag) +); + +//---------------------------------------------------------------------- +// Internal Regs and Nets +//---------------------------------------------------------------------- +reg bf_en; // Butterfly Add/Sub Enable +wire[WIDTH-1:0] x0_re; // Data #0 to Butterfly (Real) +wire[WIDTH-1:0] x0_im; // Data #0 to Butterfly (Imag) +wire[WIDTH-1:0] x1_re; // Data #1 to Butterfly (Real) +wire[WIDTH-1:0] x1_im; // Data #1 to Butterfly (Imag) +wire[WIDTH-1:0] y0_re; // Data #0 from Butterfly (Real) +wire[WIDTH-1:0] y0_im; // Data #0 from Butterfly (Imag) +wire[WIDTH-1:0] y1_re; // Data #1 from Butterfly (Real) +wire[WIDTH-1:0] y1_im; // Data #1 from Butterfly (Imag) +wire[WIDTH-1:0] db_di_re; // Data to DelayBuffer (Real) +wire[WIDTH-1:0] db_di_im; // Data to DelayBuffer (Imag) +wire[WIDTH-1:0] db_do_re; // Data from DelayBuffer (Real) +wire[WIDTH-1:0] db_do_im; // Data from DelayBuffer (Imag) +wire[WIDTH-1:0] bf_sp_re; // Single-Path Data Output (Real) +wire[WIDTH-1:0] bf_sp_im; // Single-Path Data Output (Imag) +reg bf_sp_en; // Single-Path Data Enable + +//---------------------------------------------------------------------- +// Butterfly Add/Sub +//---------------------------------------------------------------------- +always @(posedge clock or posedge reset) begin + if (reset) begin + bf_en <= 1'b0; + end else begin + bf_en <= di_en ? ~bf_en : 1'b0; + end +end + +// Set unknown value x for verification +assign x0_re = bf_en ? db_do_re : {WIDTH{1'bx}}; +assign x0_im = bf_en ? db_do_im : {WIDTH{1'bx}}; +assign x1_re = bf_en ? di_re : {WIDTH{1'bx}}; +assign x1_im = bf_en ? di_im : {WIDTH{1'bx}}; + +Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF ( + .x0_re (x0_re ), // i + .x0_im (x0_im ), // i + .x1_re (x1_re ), // i + .x1_im (x1_im ), // i + .y0_re (y0_re ), // o + .y0_im (y0_im ), // o + .y1_re (y1_re ), // o + .y1_im (y1_im ) // o +); + +DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB ( + .clock (clock ), // i + .di_re (db_di_re ), // i + .di_im (db_di_im ), // i + .do_re (db_do_re ), // o + .do_im (db_do_im ) // o +); + +assign db_di_re = bf_en ? y1_re : di_re; +assign db_di_im = bf_en ? y1_im : di_im; +assign bf_sp_re = bf_en ? y0_re : db_do_re; +assign bf_sp_im = bf_en ? y0_im : db_do_im; + +always @(posedge clock or posedge reset) begin + if (reset) begin + bf_sp_en <= 1'b0; + do_en <= 1'b0; + end else begin + bf_sp_en <= di_en; + do_en <= bf_sp_en; + end +end + +always @(posedge clock) begin + do_re <= bf_sp_re; + do_im <= bf_sp_im; +end + +endmodule diff --git a/hardware/system/Twiddle1024_32B.v b/hardware/system/Twiddle1024_32B.v new file mode 100644 index 0000000..e4952f5 --- /dev/null +++ b/hardware/system/Twiddle1024_32B.v @@ -0,0 +1,1064 @@ +//---------------------------------------------------------------------- +// Twiddle: 1024-Point Twiddle Table for Radix-2^2 Butterfly +//---------------------------------------------------------------------- +module Twiddle #( + parameter TW_FF = 1 // Use Output Register +)( + input clock, // Master Clock + input [9:0] addr, // Twiddle Factor Number + output [31:0] tw_re, // Twiddle Factor (Real) + output [31:0] tw_im // Twiddle Factor (Imag) +); + +wire[31:0] wn_re[0:1023]; // Twiddle Table (Real) +wire[31:0] wn_im[0:1023]; // Twiddle Table (Imag) +wire[31:0] mx_re; // Multiplexer output (Real) +wire[31:0] mx_im; // Multiplexer output (Imag) +reg [31:0] ff_re; // Register output (Real) +reg [31:0] ff_im; // Register output (Imag) + +assign mx_re = wn_re[addr]; +assign mx_im = wn_im[addr]; + +always @(posedge clock) begin + ff_re <= mx_re; + ff_im <= mx_im; +end + +assign tw_re = TW_FF ? ff_re : mx_re; +assign tw_im = TW_FF ? ff_im : mx_im; + +//---------------------------------------------------------------------- +// Twiddle Factor Value +//---------------------------------------------------------------------- +// Multiplication is bypassed when twiddle address is 0. +// Setting wn_re[0] = 0 and wn_im[0] = 0 makes it easier to check the waveform. +// It may also reduce power consumption slightly. +// +// wn_re = cos(-2pi*n/1024) wn_im = sin(-2pi*n/1024) +assign wn_re[ 0] = 32'h7FFFFFFF; assign wn_im[ 0] = 32'h00000000; // 0 1.000 -0.000 +assign wn_re[ 1] = 32'h7FFF6216; assign wn_im[ 1] = 32'hFF36F078; // 1 1.000 -0.006 +assign wn_re[ 2] = 32'h7FFD885A; assign wn_im[ 2] = 32'hFE6DE2E0; // 2 1.000 -0.012 +assign wn_re[ 3] = 32'h7FFA72D1; assign wn_im[ 3] = 32'hFDA4D929; // 3 1.000 -0.018 +assign wn_re[ 4] = 32'h7FF62182; assign wn_im[ 4] = 32'hFCDBD541; // 4 1.000 -0.025 +assign wn_re[ 5] = 32'h7FF09478; assign wn_im[ 5] = 32'hFC12D91A; // 5 1.000 -0.031 +assign wn_re[ 6] = 32'h7FE9CBC0; assign wn_im[ 6] = 32'hFB49E6A3; // 6 0.999 -0.037 +assign wn_re[ 7] = 32'h7FE1C76B; assign wn_im[ 7] = 32'hFA80FFCB; // 7 0.999 -0.043 +assign wn_re[ 8] = 32'h7FD8878E; assign wn_im[ 8] = 32'hF9B82684; // 8 0.999 -0.049 +assign wn_re[ 9] = 32'h7FCE0C3E; assign wn_im[ 9] = 32'hF8EF5CBB; // 9 0.998 -0.055 +assign wn_re[10] = 32'h7FC25596; assign wn_im[10] = 32'hF826A462; // 10 0.998 -0.061 +assign wn_re[11] = 32'h7FB563B3; assign wn_im[11] = 32'hF75DFF66; // 11 0.998 -0.067 +assign wn_re[12] = 32'h7FA736B4; assign wn_im[12] = 32'hF6956FB7; // 12 0.997 -0.074 +assign wn_re[13] = 32'h7F97CEBD; assign wn_im[13] = 32'hF5CCF743; // 13 0.997 -0.080 +assign wn_re[14] = 32'h7F872BF3; assign wn_im[14] = 32'hF50497FB; // 14 0.996 -0.086 +assign wn_re[15] = 32'h7F754E80; assign wn_im[15] = 32'hF43C53CB; // 15 0.996 -0.092 +assign wn_re[16] = 32'h7F62368F; assign wn_im[16] = 32'hF3742CA2; // 16 0.995 -0.098 +assign wn_re[17] = 32'h7F4DE451; assign wn_im[17] = 32'hF2AC246E; // 17 0.995 -0.104 +assign wn_re[18] = 32'h7F3857F6; assign wn_im[18] = 32'hF1E43D1C; // 18 0.994 -0.110 +assign wn_re[19] = 32'h7F2191B4; assign wn_im[19] = 32'hF11C789A; // 19 0.993 -0.116 +assign wn_re[20] = 32'h7F0991C4; assign wn_im[20] = 32'hF054D8D5; // 20 0.992 -0.122 +assign wn_re[21] = 32'h7EF05860; assign wn_im[21] = 32'hEF8D5FB8; // 21 0.992 -0.128 +assign wn_re[22] = 32'h7ED5E5C6; assign wn_im[22] = 32'hEEC60F31; // 22 0.991 -0.135 +assign wn_re[23] = 32'h7EBA3A39; assign wn_im[23] = 32'hEDFEE92B; // 23 0.990 -0.141 +assign wn_re[24] = 32'h7E9D55FC; assign wn_im[24] = 32'hED37EF91; // 24 0.989 -0.147 +assign wn_re[25] = 32'h7E7F3957; assign wn_im[25] = 32'hEC71244F; // 25 0.988 -0.153 +assign wn_re[26] = 32'h7E5FE493; assign wn_im[26] = 32'hEBAA894F; // 26 0.987 -0.159 +assign wn_re[27] = 32'h7E3F57FF; assign wn_im[27] = 32'hEAE4207A; // 27 0.986 -0.165 +assign wn_re[28] = 32'h7E1D93EA; assign wn_im[28] = 32'hEA1DEBBB; // 28 0.985 -0.171 +assign wn_re[29] = 32'h7DFA98A8; assign wn_im[29] = 32'hE957ECFB; // 29 0.984 -0.177 +assign wn_re[30] = 32'h7DD6668F; assign wn_im[30] = 32'hE8922622; // 30 0.983 -0.183 +assign wn_re[31] = 32'h7DB0FDF8; assign wn_im[31] = 32'hE7CC9917; // 31 0.982 -0.189 +assign wn_re[32] = 32'h7D8A5F40; assign wn_im[32] = 32'hE70747C4; // 32 0.981 -0.195 +assign wn_re[33] = 32'h7D628AC6; assign wn_im[33] = 32'hE642340D; // 33 0.980 -0.201 +assign wn_re[34] = 32'h7D3980EC; assign wn_im[34] = 32'hE57D5FDA; // 34 0.978 -0.207 +assign wn_re[35] = 32'h7D0F4218; assign wn_im[35] = 32'hE4B8CD11; // 35 0.977 -0.213 +assign wn_re[36] = 32'h7CE3CEB2; assign wn_im[36] = 32'hE3F47D96; // 36 0.976 -0.219 +assign wn_re[37] = 32'h7CB72724; assign wn_im[37] = 32'hE330734D; // 37 0.974 -0.225 +assign wn_re[38] = 32'h7C894BDE; assign wn_im[38] = 32'hE26CB01B; // 38 0.973 -0.231 +assign wn_re[39] = 32'h7C5A3D50; assign wn_im[39] = 32'hE1A935E2; // 39 0.972 -0.237 +assign wn_re[40] = 32'h7C29FBEE; assign wn_im[40] = 32'hE0E60685; // 40 0.970 -0.243 +assign wn_re[41] = 32'h7BF88830; assign wn_im[41] = 32'hE02323E5; // 41 0.969 -0.249 +assign wn_re[42] = 32'h7BC5E290; assign wn_im[42] = 32'hDF608FE4; // 42 0.967 -0.255 +assign wn_re[43] = 32'h7B920B89; assign wn_im[43] = 32'hDE9E4C60; // 43 0.965 -0.261 +assign wn_re[44] = 32'h7B5D039E; assign wn_im[44] = 32'hDDDC5B3B; // 44 0.964 -0.267 +assign wn_re[45] = 32'h7B26CB4F; assign wn_im[45] = 32'hDD1ABE51; // 45 0.962 -0.273 +assign wn_re[46] = 32'h7AEF6323; assign wn_im[46] = 32'hDC597781; // 46 0.960 -0.279 +assign wn_re[47] = 32'h7AB6CBA4; assign wn_im[47] = 32'hDB9888A8; // 47 0.959 -0.284 +assign wn_re[48] = 32'h7A7D055B; assign wn_im[48] = 32'hDAD7F3A2; // 48 0.957 -0.290 +assign wn_re[49] = 32'h7A4210D8; assign wn_im[49] = 32'hDA17BA4A; // 49 0.955 -0.296 +assign wn_re[50] = 32'h7A05EEAD; assign wn_im[50] = 32'hD957DE7A; // 50 0.953 -0.302 +assign wn_re[51] = 32'h79C89F6E; assign wn_im[51] = 32'hD898620C; // 51 0.951 -0.308 +assign wn_re[52] = 32'h798A23B1; assign wn_im[52] = 32'hD7D946D8; // 52 0.950 -0.314 +assign wn_re[53] = 32'h794A7C12; assign wn_im[53] = 32'hD71A8EB5; // 53 0.948 -0.320 +assign wn_re[54] = 32'h7909A92D; assign wn_im[54] = 32'hD65C3B7B; // 54 0.946 -0.325 +assign wn_re[55] = 32'h78C7ABA2; assign wn_im[55] = 32'hD59E4EFF; // 55 0.944 -0.331 +assign wn_re[56] = 32'h78848414; assign wn_im[56] = 32'hD4E0CB15; // 56 0.942 -0.337 +assign wn_re[57] = 32'h78403329; assign wn_im[57] = 32'hD423B191; // 57 0.939 -0.343 +assign wn_re[58] = 32'h77FAB989; assign wn_im[58] = 32'hD3670446; // 58 0.937 -0.348 +assign wn_re[59] = 32'h77B417DF; assign wn_im[59] = 32'hD2AAC504; // 59 0.935 -0.354 +assign wn_re[60] = 32'h776C4EDB; assign wn_im[60] = 32'hD1EEF59E; // 60 0.933 -0.360 +assign wn_re[61] = 32'h77235F2D; assign wn_im[61] = 32'hD13397E2; // 61 0.931 -0.366 +assign wn_re[62] = 32'h76D94989; assign wn_im[62] = 32'hD078AD9E; // 62 0.929 -0.371 +assign wn_re[63] = 32'h768E0EA6; assign wn_im[63] = 32'hCFBE389F; // 63 0.926 -0.377 +assign wn_re[64] = 32'h7641AF3D; assign wn_im[64] = 32'hCF043AB3; // 64 0.924 -0.383 +assign wn_re[65] = 32'h75F42C0B; assign wn_im[65] = 32'hCE4AB5A2; // 65 0.922 -0.388 +assign wn_re[66] = 32'h75A585CF; assign wn_im[66] = 32'hCD91AB39; // 66 0.919 -0.394 +assign wn_re[67] = 32'h7555BD4C; assign wn_im[67] = 32'hCCD91D3D; // 67 0.917 -0.400 +assign wn_re[68] = 32'h7504D345; assign wn_im[68] = 32'hCC210D79; // 68 0.914 -0.405 +assign wn_re[69] = 32'h74B2C884; assign wn_im[69] = 32'hCB697DB0; // 69 0.912 -0.411 +assign wn_re[70] = 32'h745F9DD1; assign wn_im[70] = 32'hCAB26FA9; // 70 0.909 -0.416 +assign wn_re[71] = 32'h740B53FB; assign wn_im[71] = 32'hC9FBE527; // 71 0.907 -0.422 +assign wn_re[72] = 32'h73B5EBD1; assign wn_im[72] = 32'hC945DFEC; // 72 0.904 -0.428 +assign wn_re[73] = 32'h735F6626; assign wn_im[73] = 32'hC89061BA; // 73 0.901 -0.433 +assign wn_re[74] = 32'h7307C3D0; assign wn_im[74] = 32'hC7DB6C50; // 74 0.899 -0.439 +assign wn_re[75] = 32'h72AF05A7; assign wn_im[75] = 32'hC727016D; // 75 0.896 -0.444 +assign wn_re[76] = 32'h72552C85; assign wn_im[76] = 32'hC67322CE; // 76 0.893 -0.450 +assign wn_re[77] = 32'h71FA3949; assign wn_im[77] = 32'hC5BFD22E; // 77 0.890 -0.455 +assign wn_re[78] = 32'h719E2CD2; assign wn_im[78] = 32'hC50D1149; // 78 0.888 -0.461 +assign wn_re[79] = 32'h71410805; assign wn_im[79] = 32'hC45AE1D7; // 79 0.885 -0.466 +assign wn_re[80] = 32'h70E2CBC6; assign wn_im[80] = 32'hC3A94590; // 80 0.882 -0.471 +assign wn_re[81] = 32'h708378FF; assign wn_im[81] = 32'hC2F83E2A; // 81 0.879 -0.477 +assign wn_re[82] = 32'h7023109A; assign wn_im[82] = 32'hC247CD5A; // 82 0.876 -0.482 +assign wn_re[83] = 32'h6FC19385; assign wn_im[83] = 32'hC197F4D4; // 83 0.873 -0.488 +assign wn_re[84] = 32'h6F5F02B2; assign wn_im[84] = 32'hC0E8B648; // 84 0.870 -0.493 +assign wn_re[85] = 32'h6EFB5F12; assign wn_im[85] = 32'hC03A1368; // 85 0.867 -0.498 +assign wn_re[86] = 32'h6E96A99D; assign wn_im[86] = 32'hBF8C0DE3; // 86 0.864 -0.504 +assign wn_re[87] = 32'h6E30E34A; assign wn_im[87] = 32'hBEDEA765; // 87 0.861 -0.509 +assign wn_re[88] = 32'h6DCA0D14; assign wn_im[88] = 32'hBE31E19B; // 88 0.858 -0.514 +assign wn_re[89] = 32'h6D6227FA; assign wn_im[89] = 32'hBD85BE30; // 89 0.855 -0.519 +assign wn_re[90] = 32'h6CF934FC; assign wn_im[90] = 32'hBCDA3ECB; // 90 0.851 -0.525 +assign wn_re[91] = 32'h6C8F351C; assign wn_im[91] = 32'hBC2F6513; // 91 0.848 -0.530 +assign wn_re[92] = 32'h6C242960; assign wn_im[92] = 32'hBB8532B0; // 92 0.845 -0.535 +assign wn_re[93] = 32'h6BB812D1; assign wn_im[93] = 32'hBADBA943; // 93 0.842 -0.540 +assign wn_re[94] = 32'h6B4AF279; assign wn_im[94] = 32'hBA32CA71; // 94 0.838 -0.545 +assign wn_re[95] = 32'h6ADCC964; assign wn_im[95] = 32'hB98A97D8; // 95 0.835 -0.550 +assign wn_re[96] = 32'h6A6D98A4; assign wn_im[96] = 32'hB8E31319; // 96 0.831 -0.556 +assign wn_re[97] = 32'h69FD614A; assign wn_im[97] = 32'hB83C3DD1; // 97 0.828 -0.561 +assign wn_re[98] = 32'h698C246C; assign wn_im[98] = 32'hB796199B; // 98 0.825 -0.566 +assign wn_re[99] = 32'h6919E320; assign wn_im[99] = 32'hB6F0A812; // 99 0.821 -0.571 +assign wn_re[100] = 32'h68A69E81; assign wn_im[100] = 32'hB64BEACD; // 100 0.818 -0.576 +assign wn_re[101] = 32'h683257AB; assign wn_im[101] = 32'hB5A7E362; // 101 0.814 -0.581 +assign wn_re[102] = 32'h67BD0FBD; assign wn_im[102] = 32'hB5049368; // 102 0.810 -0.586 +assign wn_re[103] = 32'h6746C7D8; assign wn_im[103] = 32'hB461FC70; // 103 0.807 -0.591 +assign wn_re[104] = 32'h66CF8120; assign wn_im[104] = 32'hB3C0200C; // 104 0.803 -0.596 +assign wn_re[105] = 32'h66573CBB; assign wn_im[105] = 32'hB31EFFCC; // 105 0.800 -0.601 +assign wn_re[106] = 32'h65DDFBD3; assign wn_im[106] = 32'hB27E9D3C; // 106 0.796 -0.606 +assign wn_re[107] = 32'h6563BF92; assign wn_im[107] = 32'hB1DEF9E9; // 107 0.792 -0.610 +assign wn_re[108] = 32'h64E88926; assign wn_im[108] = 32'hB140175B; // 108 0.788 -0.615 +assign wn_re[109] = 32'h646C59BF; assign wn_im[109] = 32'hB0A1F71D; // 109 0.785 -0.620 +assign wn_re[110] = 32'h63EF3290; assign wn_im[110] = 32'hB0049AB3; // 110 0.781 -0.625 +assign wn_re[111] = 32'h637114CC; assign wn_im[111] = 32'hAF6803A2; // 111 0.777 -0.630 +assign wn_re[112] = 32'h62F201AC; assign wn_im[112] = 32'hAECC336C; // 112 0.773 -0.634 +assign wn_re[113] = 32'h6271FA69; assign wn_im[113] = 32'hAE312B92; // 113 0.769 -0.639 +assign wn_re[114] = 32'h61F1003F; assign wn_im[114] = 32'hAD96ED92; // 114 0.765 -0.644 +assign wn_re[115] = 32'h616F146C; assign wn_im[115] = 32'hACFD7AE8; // 115 0.761 -0.649 +assign wn_re[116] = 32'h60EC3830; assign wn_im[116] = 32'hAC64D510; // 116 0.757 -0.653 +assign wn_re[117] = 32'h60686CCF; assign wn_im[117] = 32'hABCCFD83; // 117 0.753 -0.658 +assign wn_re[118] = 32'h5FE3B38D; assign wn_im[118] = 32'hAB35F5B5; // 118 0.749 -0.662 +assign wn_re[119] = 32'h5F5E0DB3; assign wn_im[119] = 32'hAA9FBF1E; // 119 0.745 -0.667 +assign wn_re[120] = 32'h5ED77C8A; assign wn_im[120] = 32'hAA0A5B2E; // 120 0.741 -0.672 +assign wn_re[121] = 32'h5E50015D; assign wn_im[121] = 32'hA975CB57; // 121 0.737 -0.676 +assign wn_re[122] = 32'h5DC79D7C; assign wn_im[122] = 32'hA8E21106; // 122 0.733 -0.681 +assign wn_re[123] = 32'h5D3E5237; assign wn_im[123] = 32'hA84F2DAA; // 123 0.728 -0.685 +assign wn_re[124] = 32'h5CB420E0; assign wn_im[124] = 32'hA7BD22AC; // 124 0.724 -0.690 +assign wn_re[125] = 32'h5C290ACC; assign wn_im[125] = 32'hA72BF174; // 125 0.720 -0.694 +assign wn_re[126] = 32'h5B9D1154; assign wn_im[126] = 32'hA69B9B68; // 126 0.716 -0.698 +assign wn_re[127] = 32'h5B1035CF; assign wn_im[127] = 32'hA60C21EE; // 127 0.711 -0.703 +assign wn_re[128] = 32'h5A82799A; assign wn_im[128] = 32'hA57D8666; // 128 0.707 -0.707 +assign wn_re[129] = 32'h59F3DE12; assign wn_im[129] = 32'hA4EFCA31; // 129 0.703 -0.711 +assign wn_re[130] = 32'h59646498; assign wn_im[130] = 32'hA462EEAC; // 130 0.698 -0.716 +assign wn_re[131] = 32'h58D40E8C; assign wn_im[131] = 32'hA3D6F534; // 131 0.694 -0.720 +assign wn_re[132] = 32'h5842DD54; assign wn_im[132] = 32'hA34BDF20; // 132 0.690 -0.724 +assign wn_re[133] = 32'h57B0D256; assign wn_im[133] = 32'hA2C1ADC9; // 133 0.685 -0.728 +assign wn_re[134] = 32'h571DEEFA; assign wn_im[134] = 32'hA2386284; // 134 0.681 -0.733 +assign wn_re[135] = 32'h568A34A9; assign wn_im[135] = 32'hA1AFFEA3; // 135 0.676 -0.737 +assign wn_re[136] = 32'h55F5A4D2; assign wn_im[136] = 32'hA1288376; // 136 0.672 -0.741 +assign wn_re[137] = 32'h556040E2; assign wn_im[137] = 32'hA0A1F24D; // 137 0.667 -0.745 +assign wn_re[138] = 32'h54CA0A4B; assign wn_im[138] = 32'hA01C4C73; // 138 0.662 -0.749 +assign wn_re[139] = 32'h5433027D; assign wn_im[139] = 32'h9F979331; // 139 0.658 -0.753 +assign wn_re[140] = 32'h539B2AF0; assign wn_im[140] = 32'h9F13C7D0; // 140 0.653 -0.757 +assign wn_re[141] = 32'h53028518; assign wn_im[141] = 32'h9E90EB94; // 141 0.649 -0.761 +assign wn_re[142] = 32'h5269126E; assign wn_im[142] = 32'h9E0EFFC1; // 142 0.644 -0.765 +assign wn_re[143] = 32'h51CED46E; assign wn_im[143] = 32'h9D8E0597; // 143 0.639 -0.769 +assign wn_re[144] = 32'h5133CC94; assign wn_im[144] = 32'h9D0DFE54; // 144 0.634 -0.773 +assign wn_re[145] = 32'h5097FC5E; assign wn_im[145] = 32'h9C8EEB34; // 145 0.630 -0.777 +assign wn_re[146] = 32'h4FFB654D; assign wn_im[146] = 32'h9C10CD70; // 146 0.625 -0.781 +assign wn_re[147] = 32'h4F5E08E3; assign wn_im[147] = 32'h9B93A641; // 147 0.620 -0.785 +assign wn_re[148] = 32'h4EBFE8A5; assign wn_im[148] = 32'h9B1776DA; // 148 0.615 -0.788 +assign wn_re[149] = 32'h4E210617; assign wn_im[149] = 32'h9A9C406E; // 149 0.610 -0.792 +assign wn_re[150] = 32'h4D8162C4; assign wn_im[150] = 32'h9A22042D; // 150 0.606 -0.796 +assign wn_re[151] = 32'h4CE10034; assign wn_im[151] = 32'h99A8C345; // 151 0.601 -0.800 +assign wn_re[152] = 32'h4C3FDFF4; assign wn_im[152] = 32'h99307EE0; // 152 0.596 -0.803 +assign wn_re[153] = 32'h4B9E0390; assign wn_im[153] = 32'h98B93828; // 153 0.591 -0.807 +assign wn_re[154] = 32'h4AFB6C98; assign wn_im[154] = 32'h9842F043; // 154 0.586 -0.810 +assign wn_re[155] = 32'h4A581C9E; assign wn_im[155] = 32'h97CDA855; // 155 0.581 -0.814 +assign wn_re[156] = 32'h49B41533; assign wn_im[156] = 32'h9759617F; // 156 0.576 -0.818 +assign wn_re[157] = 32'h490F57EE; assign wn_im[157] = 32'h96E61CE0; // 157 0.571 -0.821 +assign wn_re[158] = 32'h4869E665; assign wn_im[158] = 32'h9673DB94; // 158 0.566 -0.825 +assign wn_re[159] = 32'h47C3C22F; assign wn_im[159] = 32'h96029EB6; // 159 0.561 -0.828 +assign wn_re[160] = 32'h471CECE7; assign wn_im[160] = 32'h9592675C; // 160 0.556 -0.831 +assign wn_re[161] = 32'h46756828; assign wn_im[161] = 32'h9523369C; // 161 0.550 -0.835 +assign wn_re[162] = 32'h45CD358F; assign wn_im[162] = 32'h94B50D87; // 162 0.545 -0.838 +assign wn_re[163] = 32'h452456BD; assign wn_im[163] = 32'h9447ED2F; // 163 0.540 -0.842 +assign wn_re[164] = 32'h447ACD50; assign wn_im[164] = 32'h93DBD6A0; // 164 0.535 -0.845 +assign wn_re[165] = 32'h43D09AED; assign wn_im[165] = 32'h9370CAE4; // 165 0.530 -0.848 +assign wn_re[166] = 32'h4325C135; assign wn_im[166] = 32'h9306CB04; // 166 0.525 -0.851 +assign wn_re[167] = 32'h427A41D0; assign wn_im[167] = 32'h929DD806; // 167 0.519 -0.855 +assign wn_re[168] = 32'h41CE1E65; assign wn_im[168] = 32'h9235F2EC; // 168 0.514 -0.858 +assign wn_re[169] = 32'h4121589B; assign wn_im[169] = 32'h91CF1CB6; // 169 0.509 -0.861 +assign wn_re[170] = 32'h4073F21D; assign wn_im[170] = 32'h91695663; // 170 0.504 -0.864 +assign wn_re[171] = 32'h3FC5EC98; assign wn_im[171] = 32'h9104A0EE; // 171 0.498 -0.867 +assign wn_re[172] = 32'h3F1749B8; assign wn_im[172] = 32'h90A0FD4E; // 172 0.493 -0.870 +assign wn_re[173] = 32'h3E680B2C; assign wn_im[173] = 32'h903E6C7B; // 173 0.488 -0.873 +assign wn_re[174] = 32'h3DB832A6; assign wn_im[174] = 32'h8FDCEF66; // 174 0.482 -0.876 +assign wn_re[175] = 32'h3D07C1D6; assign wn_im[175] = 32'h8F7C8701; // 175 0.477 -0.879 +assign wn_re[176] = 32'h3C56BA70; assign wn_im[176] = 32'h8F1D343A; // 176 0.471 -0.882 +assign wn_re[177] = 32'h3BA51E29; assign wn_im[177] = 32'h8EBEF7FB; // 177 0.466 -0.885 +assign wn_re[178] = 32'h3AF2EEB7; assign wn_im[178] = 32'h8E61D32E; // 178 0.461 -0.888 +assign wn_re[179] = 32'h3A402DD2; assign wn_im[179] = 32'h8E05C6B7; // 179 0.455 -0.890 +assign wn_re[180] = 32'h398CDD32; assign wn_im[180] = 32'h8DAAD37B; // 180 0.450 -0.893 +assign wn_re[181] = 32'h38D8FE93; assign wn_im[181] = 32'h8D50FA59; // 181 0.444 -0.896 +assign wn_re[182] = 32'h382493B0; assign wn_im[182] = 32'h8CF83C30; // 182 0.439 -0.899 +assign wn_re[183] = 32'h376F9E46; assign wn_im[183] = 32'h8CA099DA; // 183 0.433 -0.901 +assign wn_re[184] = 32'h36BA2014; assign wn_im[184] = 32'h8C4A142F; // 184 0.428 -0.904 +assign wn_re[185] = 32'h36041AD9; assign wn_im[185] = 32'h8BF4AC05; // 185 0.422 -0.907 +assign wn_re[186] = 32'h354D9057; assign wn_im[186] = 32'h8BA0622F; // 186 0.416 -0.909 +assign wn_re[187] = 32'h34968250; assign wn_im[187] = 32'h8B4D377C; // 187 0.411 -0.912 +assign wn_re[188] = 32'h33DEF287; assign wn_im[188] = 32'h8AFB2CBB; // 188 0.405 -0.914 +assign wn_re[189] = 32'h3326E2C3; assign wn_im[189] = 32'h8AAA42B4; // 189 0.400 -0.917 +assign wn_re[190] = 32'h326E54C7; assign wn_im[190] = 32'h8A5A7A31; // 190 0.394 -0.919 +assign wn_re[191] = 32'h31B54A5E; assign wn_im[191] = 32'h8A0BD3F5; // 191 0.388 -0.922 +assign wn_re[192] = 32'h30FBC54D; assign wn_im[192] = 32'h89BE50C3; // 192 0.383 -0.924 +assign wn_re[193] = 32'h3041C761; assign wn_im[193] = 32'h8971F15A; // 193 0.377 -0.926 +assign wn_re[194] = 32'h2F875262; assign wn_im[194] = 32'h8926B677; // 194 0.371 -0.929 +assign wn_re[195] = 32'h2ECC681E; assign wn_im[195] = 32'h88DCA0D3; // 195 0.366 -0.931 +assign wn_re[196] = 32'h2E110A62; assign wn_im[196] = 32'h8893B125; // 196 0.360 -0.933 +assign wn_re[197] = 32'h2D553AFC; assign wn_im[197] = 32'h884BE821; // 197 0.354 -0.935 +assign wn_re[198] = 32'h2C98FBBA; assign wn_im[198] = 32'h88054677; // 198 0.348 -0.937 +assign wn_re[199] = 32'h2BDC4E6F; assign wn_im[199] = 32'h87BFCCD7; // 199 0.343 -0.939 +assign wn_re[200] = 32'h2B1F34EB; assign wn_im[200] = 32'h877B7BEC; // 200 0.337 -0.942 +assign wn_re[201] = 32'h2A61B101; assign wn_im[201] = 32'h8738545E; // 201 0.331 -0.944 +assign wn_re[202] = 32'h29A3C485; assign wn_im[202] = 32'h86F656D3; // 202 0.325 -0.946 +assign wn_re[203] = 32'h28E5714B; assign wn_im[203] = 32'h86B583EE; // 203 0.320 -0.948 +assign wn_re[204] = 32'h2826B928; assign wn_im[204] = 32'h8675DC4F; // 204 0.314 -0.950 +assign wn_re[205] = 32'h27679DF4; assign wn_im[205] = 32'h86376092; // 205 0.308 -0.951 +assign wn_re[206] = 32'h26A82186; assign wn_im[206] = 32'h85FA1153; // 206 0.302 -0.953 +assign wn_re[207] = 32'h25E845B6; assign wn_im[207] = 32'h85BDEF28; // 207 0.296 -0.955 +assign wn_re[208] = 32'h25280C5E; assign wn_im[208] = 32'h8582FAA5; // 208 0.290 -0.957 +assign wn_re[209] = 32'h24677758; assign wn_im[209] = 32'h8549345C; // 209 0.284 -0.959 +assign wn_re[210] = 32'h23A6887F; assign wn_im[210] = 32'h85109CDD; // 210 0.279 -0.960 +assign wn_re[211] = 32'h22E541AF; assign wn_im[211] = 32'h84D934B1; // 211 0.273 -0.962 +assign wn_re[212] = 32'h2223A4C5; assign wn_im[212] = 32'h84A2FC62; // 212 0.267 -0.964 +assign wn_re[213] = 32'h2161B3A0; assign wn_im[213] = 32'h846DF477; // 213 0.261 -0.965 +assign wn_re[214] = 32'h209F701C; assign wn_im[214] = 32'h843A1D70; // 214 0.255 -0.967 +assign wn_re[215] = 32'h1FDCDC1B; assign wn_im[215] = 32'h840777D0; // 215 0.249 -0.969 +assign wn_re[216] = 32'h1F19F97B; assign wn_im[216] = 32'h83D60412; // 216 0.243 -0.970 +assign wn_re[217] = 32'h1E56CA1E; assign wn_im[217] = 32'h83A5C2B0; // 217 0.237 -0.972 +assign wn_re[218] = 32'h1D934FE5; assign wn_im[218] = 32'h8376B422; // 218 0.231 -0.973 +assign wn_re[219] = 32'h1CCF8CB3; assign wn_im[219] = 32'h8348D8DC; // 219 0.225 -0.974 +assign wn_re[220] = 32'h1C0B826A; assign wn_im[220] = 32'h831C314E; // 220 0.219 -0.976 +assign wn_re[221] = 32'h1B4732EF; assign wn_im[221] = 32'h82F0BDE8; // 221 0.213 -0.977 +assign wn_re[222] = 32'h1A82A026; assign wn_im[222] = 32'h82C67F14; // 222 0.207 -0.978 +assign wn_re[223] = 32'h19BDCBF3; assign wn_im[223] = 32'h829D753A; // 223 0.201 -0.980 +assign wn_re[224] = 32'h18F8B83C; assign wn_im[224] = 32'h8275A0C0; // 224 0.195 -0.981 +assign wn_re[225] = 32'h183366E9; assign wn_im[225] = 32'h824F0208; // 225 0.189 -0.982 +assign wn_re[226] = 32'h176DD9DE; assign wn_im[226] = 32'h82299971; // 226 0.183 -0.983 +assign wn_re[227] = 32'h16A81305; assign wn_im[227] = 32'h82056758; // 227 0.177 -0.984 +assign wn_re[228] = 32'h15E21445; assign wn_im[228] = 32'h81E26C16; // 228 0.171 -0.985 +assign wn_re[229] = 32'h151BDF86; assign wn_im[229] = 32'h81C0A801; // 229 0.165 -0.986 +assign wn_re[230] = 32'h145576B1; assign wn_im[230] = 32'h81A01B6D; // 230 0.159 -0.987 +assign wn_re[231] = 32'h138EDBB1; assign wn_im[231] = 32'h8180C6A9; // 231 0.153 -0.988 +assign wn_re[232] = 32'h12C8106F; assign wn_im[232] = 32'h8162AA04; // 232 0.147 -0.989 +assign wn_re[233] = 32'h120116D5; assign wn_im[233] = 32'h8145C5C7; // 233 0.141 -0.990 +assign wn_re[234] = 32'h1139F0CF; assign wn_im[234] = 32'h812A1A3A; // 234 0.135 -0.991 +assign wn_re[235] = 32'h1072A048; assign wn_im[235] = 32'h810FA7A0; // 235 0.128 -0.992 +assign wn_re[236] = 32'h0FAB272B; assign wn_im[236] = 32'h80F66E3C; // 236 0.122 -0.992 +assign wn_re[237] = 32'h0EE38766; assign wn_im[237] = 32'h80DE6E4C; // 237 0.116 -0.993 +assign wn_re[238] = 32'h0E1BC2E4; assign wn_im[238] = 32'h80C7A80A; // 238 0.110 -0.994 +assign wn_re[239] = 32'h0D53DB92; assign wn_im[239] = 32'h80B21BAF; // 239 0.104 -0.995 +assign wn_re[240] = 32'h0C8BD35E; assign wn_im[240] = 32'h809DC971; // 240 0.098 -0.995 +assign wn_re[241] = 32'h0BC3AC35; assign wn_im[241] = 32'h808AB180; // 241 0.092 -0.996 +assign wn_re[242] = 32'h0AFB6805; assign wn_im[242] = 32'h8078D40D; // 242 0.086 -0.996 +assign wn_re[243] = 32'h0A3308BD; assign wn_im[243] = 32'h80683143; // 243 0.080 -0.997 +assign wn_re[244] = 32'h096A9049; assign wn_im[244] = 32'h8058C94C; // 244 0.074 -0.997 +assign wn_re[245] = 32'h08A2009A; assign wn_im[245] = 32'h804A9C4D; // 245 0.067 -0.998 +assign wn_re[246] = 32'h07D95B9E; assign wn_im[246] = 32'h803DAA6A; // 246 0.061 -0.998 +assign wn_re[247] = 32'h0710A345; assign wn_im[247] = 32'h8031F3C2; // 247 0.055 -0.998 +assign wn_re[248] = 32'h0647D97C; assign wn_im[248] = 32'h80277872; // 248 0.049 -0.999 +assign wn_re[249] = 32'h057F0035; assign wn_im[249] = 32'h801E3895; // 249 0.043 -0.999 +assign wn_re[250] = 32'h04B6195D; assign wn_im[250] = 32'h80163440; // 250 0.037 -0.999 +assign wn_re[251] = 32'h03ED26E6; assign wn_im[251] = 32'h800F6B88; // 251 0.031 -1.000 +assign wn_re[252] = 32'h03242ABF; assign wn_im[252] = 32'h8009DE7E; // 252 0.025 -1.000 +assign wn_re[253] = 32'h025B26D7; assign wn_im[253] = 32'h80058D2F; // 253 0.018 -1.000 +assign wn_re[254] = 32'h01921D20; assign wn_im[254] = 32'h800277A6; // 254 0.012 -1.000 +assign wn_re[255] = 32'h00C90F88; assign wn_im[255] = 32'h80009DEA; // 255 0.006 -1.000 +assign wn_re[256] = 32'h00000000; assign wn_im[256] = 32'h80000000; // 256 0.000 -1.000 +assign wn_re[257] = 32'hFF36F078; assign wn_im[257] = 32'h80009DEA; // 257 -0.006 -1.000 +assign wn_re[258] = 32'hFE6DE2E0; assign wn_im[258] = 32'h800277A6; // 258 -0.012 -1.000 +assign wn_re[259] = 32'hFDA4D929; assign wn_im[259] = 32'h80058D2F; // 259 -0.018 -1.000 +assign wn_re[260] = 32'hFCDBD541; assign wn_im[260] = 32'h8009DE7E; // 260 -0.025 -1.000 +assign wn_re[261] = 32'hFC12D91A; assign wn_im[261] = 32'h800F6B88; // 261 -0.031 -1.000 +assign wn_re[262] = 32'hFB49E6A3; assign wn_im[262] = 32'h80163440; // 262 -0.037 -0.999 +assign wn_re[263] = 32'hFA80FFCB; assign wn_im[263] = 32'h801E3895; // 263 -0.043 -0.999 +assign wn_re[264] = 32'hF9B82684; assign wn_im[264] = 32'h80277872; // 264 -0.049 -0.999 +assign wn_re[265] = 32'hF8EF5CBB; assign wn_im[265] = 32'h8031F3C2; // 265 -0.055 -0.998 +assign wn_re[266] = 32'hF826A462; assign wn_im[266] = 32'h803DAA6A; // 266 -0.061 -0.998 +assign wn_re[267] = 32'hF75DFF66; assign wn_im[267] = 32'h804A9C4D; // 267 -0.067 -0.998 +assign wn_re[268] = 32'hF6956FB7; assign wn_im[268] = 32'h8058C94C; // 268 -0.074 -0.997 +assign wn_re[269] = 32'hF5CCF743; assign wn_im[269] = 32'h80683143; // 269 -0.080 -0.997 +assign wn_re[270] = 32'hF50497FB; assign wn_im[270] = 32'h8078D40D; // 270 -0.086 -0.996 +assign wn_re[271] = 32'hF43C53CB; assign wn_im[271] = 32'h808AB180; // 271 -0.092 -0.996 +assign wn_re[272] = 32'hF3742CA2; assign wn_im[272] = 32'h809DC971; // 272 -0.098 -0.995 +assign wn_re[273] = 32'hF2AC246E; assign wn_im[273] = 32'h80B21BAF; // 273 -0.104 -0.995 +assign wn_re[274] = 32'hF1E43D1C; assign wn_im[274] = 32'h80C7A80A; // 274 -0.110 -0.994 +assign wn_re[275] = 32'hF11C789A; assign wn_im[275] = 32'h80DE6E4C; // 275 -0.116 -0.993 +assign wn_re[276] = 32'hF054D8D5; assign wn_im[276] = 32'h80F66E3C; // 276 -0.122 -0.992 +assign wn_re[277] = 32'hEF8D5FB8; assign wn_im[277] = 32'h810FA7A0; // 277 -0.128 -0.992 +assign wn_re[278] = 32'hEEC60F31; assign wn_im[278] = 32'h812A1A3A; // 278 -0.135 -0.991 +assign wn_re[279] = 32'hEDFEE92B; assign wn_im[279] = 32'h8145C5C7; // 279 -0.141 -0.990 +assign wn_re[280] = 32'hED37EF91; assign wn_im[280] = 32'h8162AA04; // 280 -0.147 -0.989 +assign wn_re[281] = 32'hEC71244F; assign wn_im[281] = 32'h8180C6A9; // 281 -0.153 -0.988 +assign wn_re[282] = 32'hEBAA894F; assign wn_im[282] = 32'h81A01B6D; // 282 -0.159 -0.987 +assign wn_re[283] = 32'hEAE4207A; assign wn_im[283] = 32'h81C0A801; // 283 -0.165 -0.986 +assign wn_re[284] = 32'hEA1DEBBB; assign wn_im[284] = 32'h81E26C16; // 284 -0.171 -0.985 +assign wn_re[285] = 32'hE957ECFB; assign wn_im[285] = 32'h82056758; // 285 -0.177 -0.984 +assign wn_re[286] = 32'hE8922622; assign wn_im[286] = 32'h82299971; // 286 -0.183 -0.983 +assign wn_re[287] = 32'hE7CC9917; assign wn_im[287] = 32'h824F0208; // 287 -0.189 -0.982 +assign wn_re[288] = 32'hE70747C4; assign wn_im[288] = 32'h8275A0C0; // 288 -0.195 -0.981 +assign wn_re[289] = 32'hE642340D; assign wn_im[289] = 32'h829D753A; // 289 -0.201 -0.980 +assign wn_re[290] = 32'hE57D5FDA; assign wn_im[290] = 32'h82C67F14; // 290 -0.207 -0.978 +assign wn_re[291] = 32'hE4B8CD11; assign wn_im[291] = 32'h82F0BDE8; // 291 -0.213 -0.977 +assign wn_re[292] = 32'hE3F47D96; assign wn_im[292] = 32'h831C314E; // 292 -0.219 -0.976 +assign wn_re[293] = 32'hE330734D; assign wn_im[293] = 32'h8348D8DC; // 293 -0.225 -0.974 +assign wn_re[294] = 32'hE26CB01B; assign wn_im[294] = 32'h8376B422; // 294 -0.231 -0.973 +assign wn_re[295] = 32'hE1A935E2; assign wn_im[295] = 32'h83A5C2B0; // 295 -0.237 -0.972 +assign wn_re[296] = 32'hE0E60685; assign wn_im[296] = 32'h83D60412; // 296 -0.243 -0.970 +assign wn_re[297] = 32'hE02323E5; assign wn_im[297] = 32'h840777D0; // 297 -0.249 -0.969 +assign wn_re[298] = 32'hDF608FE4; assign wn_im[298] = 32'h843A1D70; // 298 -0.255 -0.967 +assign wn_re[299] = 32'hDE9E4C60; assign wn_im[299] = 32'h846DF477; // 299 -0.261 -0.965 +assign wn_re[300] = 32'hDDDC5B3B; assign wn_im[300] = 32'h84A2FC62; // 300 -0.267 -0.964 +assign wn_re[301] = 32'hDD1ABE51; assign wn_im[301] = 32'h84D934B1; // 301 -0.273 -0.962 +assign wn_re[302] = 32'hDC597781; assign wn_im[302] = 32'h85109CDD; // 302 -0.279 -0.960 +assign wn_re[303] = 32'hDB9888A8; assign wn_im[303] = 32'h8549345C; // 303 -0.284 -0.959 +assign wn_re[304] = 32'hDAD7F3A2; assign wn_im[304] = 32'h8582FAA5; // 304 -0.290 -0.957 +assign wn_re[305] = 32'hDA17BA4A; assign wn_im[305] = 32'h85BDEF28; // 305 -0.296 -0.955 +assign wn_re[306] = 32'hD957DE7A; assign wn_im[306] = 32'h85FA1153; // 306 -0.302 -0.953 +assign wn_re[307] = 32'hD898620C; assign wn_im[307] = 32'h86376092; // 307 -0.308 -0.951 +assign wn_re[308] = 32'hD7D946D8; assign wn_im[308] = 32'h8675DC4F; // 308 -0.314 -0.950 +assign wn_re[309] = 32'hD71A8EB5; assign wn_im[309] = 32'h86B583EE; // 309 -0.320 -0.948 +assign wn_re[310] = 32'hD65C3B7B; assign wn_im[310] = 32'h86F656D3; // 310 -0.325 -0.946 +assign wn_re[311] = 32'hD59E4EFF; assign wn_im[311] = 32'h8738545E; // 311 -0.331 -0.944 +assign wn_re[312] = 32'hD4E0CB15; assign wn_im[312] = 32'h877B7BEC; // 312 -0.337 -0.942 +assign wn_re[313] = 32'hD423B191; assign wn_im[313] = 32'h87BFCCD7; // 313 -0.343 -0.939 +assign wn_re[314] = 32'hD3670446; assign wn_im[314] = 32'h88054677; // 314 -0.348 -0.937 +assign wn_re[315] = 32'hD2AAC504; assign wn_im[315] = 32'h884BE821; // 315 -0.354 -0.935 +assign wn_re[316] = 32'hD1EEF59E; assign wn_im[316] = 32'h8893B125; // 316 -0.360 -0.933 +assign wn_re[317] = 32'hD13397E2; assign wn_im[317] = 32'h88DCA0D3; // 317 -0.366 -0.931 +assign wn_re[318] = 32'hD078AD9E; assign wn_im[318] = 32'h8926B677; // 318 -0.371 -0.929 +assign wn_re[319] = 32'hCFBE389F; assign wn_im[319] = 32'h8971F15A; // 319 -0.377 -0.926 +assign wn_re[320] = 32'hCF043AB3; assign wn_im[320] = 32'h89BE50C3; // 320 -0.383 -0.924 +assign wn_re[321] = 32'hCE4AB5A2; assign wn_im[321] = 32'h8A0BD3F5; // 321 -0.388 -0.922 +assign wn_re[322] = 32'hCD91AB39; assign wn_im[322] = 32'h8A5A7A31; // 322 -0.394 -0.919 +assign wn_re[323] = 32'hCCD91D3D; assign wn_im[323] = 32'h8AAA42B4; // 323 -0.400 -0.917 +assign wn_re[324] = 32'hCC210D79; assign wn_im[324] = 32'h8AFB2CBB; // 324 -0.405 -0.914 +assign wn_re[325] = 32'hCB697DB0; assign wn_im[325] = 32'h8B4D377C; // 325 -0.411 -0.912 +assign wn_re[326] = 32'hCAB26FA9; assign wn_im[326] = 32'h8BA0622F; // 326 -0.416 -0.909 +assign wn_re[327] = 32'hC9FBE527; assign wn_im[327] = 32'h8BF4AC05; // 327 -0.422 -0.907 +assign wn_re[328] = 32'hC945DFEC; assign wn_im[328] = 32'h8C4A142F; // 328 -0.428 -0.904 +assign wn_re[329] = 32'hC89061BA; assign wn_im[329] = 32'h8CA099DA; // 329 -0.433 -0.901 +assign wn_re[330] = 32'hC7DB6C50; assign wn_im[330] = 32'h8CF83C30; // 330 -0.439 -0.899 +assign wn_re[331] = 32'hC727016D; assign wn_im[331] = 32'h8D50FA59; // 331 -0.444 -0.896 +assign wn_re[332] = 32'hC67322CE; assign wn_im[332] = 32'h8DAAD37B; // 332 -0.450 -0.893 +assign wn_re[333] = 32'hC5BFD22E; assign wn_im[333] = 32'h8E05C6B7; // 333 -0.455 -0.890 +assign wn_re[334] = 32'hC50D1149; assign wn_im[334] = 32'h8E61D32E; // 334 -0.461 -0.888 +assign wn_re[335] = 32'hC45AE1D7; assign wn_im[335] = 32'h8EBEF7FB; // 335 -0.466 -0.885 +assign wn_re[336] = 32'hC3A94590; assign wn_im[336] = 32'h8F1D343A; // 336 -0.471 -0.882 +assign wn_re[337] = 32'hC2F83E2A; assign wn_im[337] = 32'h8F7C8701; // 337 -0.477 -0.879 +assign wn_re[338] = 32'hC247CD5A; assign wn_im[338] = 32'h8FDCEF66; // 338 -0.482 -0.876 +assign wn_re[339] = 32'hC197F4D4; assign wn_im[339] = 32'h903E6C7B; // 339 -0.488 -0.873 +assign wn_re[340] = 32'hC0E8B648; assign wn_im[340] = 32'h90A0FD4E; // 340 -0.493 -0.870 +assign wn_re[341] = 32'hC03A1368; assign wn_im[341] = 32'h9104A0EE; // 341 -0.498 -0.867 +assign wn_re[342] = 32'hBF8C0DE3; assign wn_im[342] = 32'h91695663; // 342 -0.504 -0.864 +assign wn_re[343] = 32'hBEDEA765; assign wn_im[343] = 32'h91CF1CB6; // 343 -0.509 -0.861 +assign wn_re[344] = 32'hBE31E19B; assign wn_im[344] = 32'h9235F2EC; // 344 -0.514 -0.858 +assign wn_re[345] = 32'hBD85BE30; assign wn_im[345] = 32'h929DD806; // 345 -0.519 -0.855 +assign wn_re[346] = 32'hBCDA3ECB; assign wn_im[346] = 32'h9306CB04; // 346 -0.525 -0.851 +assign wn_re[347] = 32'hBC2F6513; assign wn_im[347] = 32'h9370CAE4; // 347 -0.530 -0.848 +assign wn_re[348] = 32'hBB8532B0; assign wn_im[348] = 32'h93DBD6A0; // 348 -0.535 -0.845 +assign wn_re[349] = 32'hBADBA943; assign wn_im[349] = 32'h9447ED2F; // 349 -0.540 -0.842 +assign wn_re[350] = 32'hBA32CA71; assign wn_im[350] = 32'h94B50D87; // 350 -0.545 -0.838 +assign wn_re[351] = 32'hB98A97D8; assign wn_im[351] = 32'h9523369C; // 351 -0.550 -0.835 +assign wn_re[352] = 32'hB8E31319; assign wn_im[352] = 32'h9592675C; // 352 -0.556 -0.831 +assign wn_re[353] = 32'hB83C3DD1; assign wn_im[353] = 32'h96029EB6; // 353 -0.561 -0.828 +assign wn_re[354] = 32'hB796199B; assign wn_im[354] = 32'h9673DB94; // 354 -0.566 -0.825 +assign wn_re[355] = 32'hB6F0A812; assign wn_im[355] = 32'h96E61CE0; // 355 -0.571 -0.821 +assign wn_re[356] = 32'hB64BEACD; assign wn_im[356] = 32'h9759617F; // 356 -0.576 -0.818 +assign wn_re[357] = 32'hB5A7E362; assign wn_im[357] = 32'h97CDA855; // 357 -0.581 -0.814 +assign wn_re[358] = 32'hB5049368; assign wn_im[358] = 32'h9842F043; // 358 -0.586 -0.810 +assign wn_re[359] = 32'hB461FC70; assign wn_im[359] = 32'h98B93828; // 359 -0.591 -0.807 +assign wn_re[360] = 32'hB3C0200C; assign wn_im[360] = 32'h99307EE0; // 360 -0.596 -0.803 +assign wn_re[361] = 32'hB31EFFCC; assign wn_im[361] = 32'h99A8C345; // 361 -0.601 -0.800 +assign wn_re[362] = 32'hB27E9D3C; assign wn_im[362] = 32'h9A22042D; // 362 -0.606 -0.796 +assign wn_re[363] = 32'hB1DEF9E9; assign wn_im[363] = 32'h9A9C406E; // 363 -0.610 -0.792 +assign wn_re[364] = 32'hB140175B; assign wn_im[364] = 32'h9B1776DA; // 364 -0.615 -0.788 +assign wn_re[365] = 32'hB0A1F71D; assign wn_im[365] = 32'h9B93A641; // 365 -0.620 -0.785 +assign wn_re[366] = 32'hB0049AB3; assign wn_im[366] = 32'h9C10CD70; // 366 -0.625 -0.781 +assign wn_re[367] = 32'hAF6803A2; assign wn_im[367] = 32'h9C8EEB34; // 367 -0.630 -0.777 +assign wn_re[368] = 32'hAECC336C; assign wn_im[368] = 32'h9D0DFE54; // 368 -0.634 -0.773 +assign wn_re[369] = 32'hAE312B92; assign wn_im[369] = 32'h9D8E0597; // 369 -0.639 -0.769 +assign wn_re[370] = 32'hAD96ED92; assign wn_im[370] = 32'h9E0EFFC1; // 370 -0.644 -0.765 +assign wn_re[371] = 32'hACFD7AE8; assign wn_im[371] = 32'h9E90EB94; // 371 -0.649 -0.761 +assign wn_re[372] = 32'hAC64D510; assign wn_im[372] = 32'h9F13C7D0; // 372 -0.653 -0.757 +assign wn_re[373] = 32'hABCCFD83; assign wn_im[373] = 32'h9F979331; // 373 -0.658 -0.753 +assign wn_re[374] = 32'hAB35F5B5; assign wn_im[374] = 32'hA01C4C73; // 374 -0.662 -0.749 +assign wn_re[375] = 32'hAA9FBF1E; assign wn_im[375] = 32'hA0A1F24D; // 375 -0.667 -0.745 +assign wn_re[376] = 32'hAA0A5B2E; assign wn_im[376] = 32'hA1288376; // 376 -0.672 -0.741 +assign wn_re[377] = 32'hA975CB57; assign wn_im[377] = 32'hA1AFFEA3; // 377 -0.676 -0.737 +assign wn_re[378] = 32'hA8E21106; assign wn_im[378] = 32'hA2386284; // 378 -0.681 -0.733 +assign wn_re[379] = 32'hA84F2DAA; assign wn_im[379] = 32'hA2C1ADC9; // 379 -0.685 -0.728 +assign wn_re[380] = 32'hA7BD22AC; assign wn_im[380] = 32'hA34BDF20; // 380 -0.690 -0.724 +assign wn_re[381] = 32'hA72BF174; assign wn_im[381] = 32'hA3D6F534; // 381 -0.694 -0.720 +assign wn_re[382] = 32'hA69B9B68; assign wn_im[382] = 32'hA462EEAC; // 382 -0.698 -0.716 +assign wn_re[383] = 32'hA60C21EE; assign wn_im[383] = 32'hA4EFCA31; // 383 -0.703 -0.711 +assign wn_re[384] = 32'hA57D8666; assign wn_im[384] = 32'hA57D8666; // 384 -0.707 -0.707 +assign wn_re[385] = 32'hA4EFCA31; assign wn_im[385] = 32'hA60C21EE; // 385 -0.711 -0.703 +assign wn_re[386] = 32'hA462EEAC; assign wn_im[386] = 32'hA69B9B68; // 386 -0.716 -0.698 +assign wn_re[387] = 32'hA3D6F534; assign wn_im[387] = 32'hA72BF174; // 387 -0.720 -0.694 +assign wn_re[388] = 32'hA34BDF20; assign wn_im[388] = 32'hA7BD22AC; // 388 -0.724 -0.690 +assign wn_re[389] = 32'hA2C1ADC9; assign wn_im[389] = 32'hA84F2DAA; // 389 -0.728 -0.685 +assign wn_re[390] = 32'hA2386284; assign wn_im[390] = 32'hA8E21106; // 390 -0.733 -0.681 +assign wn_re[391] = 32'hA1AFFEA3; assign wn_im[391] = 32'hA975CB57; // 391 -0.737 -0.676 +assign wn_re[392] = 32'hA1288376; assign wn_im[392] = 32'hAA0A5B2E; // 392 -0.741 -0.672 +assign wn_re[393] = 32'hA0A1F24D; assign wn_im[393] = 32'hAA9FBF1E; // 393 -0.745 -0.667 +assign wn_re[394] = 32'hA01C4C73; assign wn_im[394] = 32'hAB35F5B5; // 394 -0.749 -0.662 +assign wn_re[395] = 32'h9F979331; assign wn_im[395] = 32'hABCCFD83; // 395 -0.753 -0.658 +assign wn_re[396] = 32'h9F13C7D0; assign wn_im[396] = 32'hAC64D510; // 396 -0.757 -0.653 +assign wn_re[397] = 32'h9E90EB94; assign wn_im[397] = 32'hACFD7AE8; // 397 -0.761 -0.649 +assign wn_re[398] = 32'h9E0EFFC1; assign wn_im[398] = 32'hAD96ED92; // 398 -0.765 -0.644 +assign wn_re[399] = 32'h9D8E0597; assign wn_im[399] = 32'hAE312B92; // 399 -0.769 -0.639 +assign wn_re[400] = 32'h9D0DFE54; assign wn_im[400] = 32'hAECC336C; // 400 -0.773 -0.634 +assign wn_re[401] = 32'h9C8EEB34; assign wn_im[401] = 32'hAF6803A2; // 401 -0.777 -0.630 +assign wn_re[402] = 32'h9C10CD70; assign wn_im[402] = 32'hB0049AB3; // 402 -0.781 -0.625 +assign wn_re[403] = 32'h9B93A641; assign wn_im[403] = 32'hB0A1F71D; // 403 -0.785 -0.620 +assign wn_re[404] = 32'h9B1776DA; assign wn_im[404] = 32'hB140175B; // 404 -0.788 -0.615 +assign wn_re[405] = 32'h9A9C406E; assign wn_im[405] = 32'hB1DEF9E9; // 405 -0.792 -0.610 +assign wn_re[406] = 32'h9A22042D; assign wn_im[406] = 32'hB27E9D3C; // 406 -0.796 -0.606 +assign wn_re[407] = 32'h99A8C345; assign wn_im[407] = 32'hB31EFFCC; // 407 -0.800 -0.601 +assign wn_re[408] = 32'h99307EE0; assign wn_im[408] = 32'hB3C0200C; // 408 -0.803 -0.596 +assign wn_re[409] = 32'h98B93828; assign wn_im[409] = 32'hB461FC70; // 409 -0.807 -0.591 +assign wn_re[410] = 32'h9842F043; assign wn_im[410] = 32'hB5049368; // 410 -0.810 -0.586 +assign wn_re[411] = 32'h97CDA855; assign wn_im[411] = 32'hB5A7E362; // 411 -0.814 -0.581 +assign wn_re[412] = 32'h9759617F; assign wn_im[412] = 32'hB64BEACD; // 412 -0.818 -0.576 +assign wn_re[413] = 32'h96E61CE0; assign wn_im[413] = 32'hB6F0A812; // 413 -0.821 -0.571 +assign wn_re[414] = 32'h9673DB94; assign wn_im[414] = 32'hB796199B; // 414 -0.825 -0.566 +assign wn_re[415] = 32'h96029EB6; assign wn_im[415] = 32'hB83C3DD1; // 415 -0.828 -0.561 +assign wn_re[416] = 32'h9592675C; assign wn_im[416] = 32'hB8E31319; // 416 -0.831 -0.556 +assign wn_re[417] = 32'h9523369C; assign wn_im[417] = 32'hB98A97D8; // 417 -0.835 -0.550 +assign wn_re[418] = 32'h94B50D87; assign wn_im[418] = 32'hBA32CA71; // 418 -0.838 -0.545 +assign wn_re[419] = 32'h9447ED2F; assign wn_im[419] = 32'hBADBA943; // 419 -0.842 -0.540 +assign wn_re[420] = 32'h93DBD6A0; assign wn_im[420] = 32'hBB8532B0; // 420 -0.845 -0.535 +assign wn_re[421] = 32'h9370CAE4; assign wn_im[421] = 32'hBC2F6513; // 421 -0.848 -0.530 +assign wn_re[422] = 32'h9306CB04; assign wn_im[422] = 32'hBCDA3ECB; // 422 -0.851 -0.525 +assign wn_re[423] = 32'h929DD806; assign wn_im[423] = 32'hBD85BE30; // 423 -0.855 -0.519 +assign wn_re[424] = 32'h9235F2EC; assign wn_im[424] = 32'hBE31E19B; // 424 -0.858 -0.514 +assign wn_re[425] = 32'h91CF1CB6; assign wn_im[425] = 32'hBEDEA765; // 425 -0.861 -0.509 +assign wn_re[426] = 32'h91695663; assign wn_im[426] = 32'hBF8C0DE3; // 426 -0.864 -0.504 +assign wn_re[427] = 32'h9104A0EE; assign wn_im[427] = 32'hC03A1368; // 427 -0.867 -0.498 +assign wn_re[428] = 32'h90A0FD4E; assign wn_im[428] = 32'hC0E8B648; // 428 -0.870 -0.493 +assign wn_re[429] = 32'h903E6C7B; assign wn_im[429] = 32'hC197F4D4; // 429 -0.873 -0.488 +assign wn_re[430] = 32'h8FDCEF66; assign wn_im[430] = 32'hC247CD5A; // 430 -0.876 -0.482 +assign wn_re[431] = 32'h8F7C8701; assign wn_im[431] = 32'hC2F83E2A; // 431 -0.879 -0.477 +assign wn_re[432] = 32'h8F1D343A; assign wn_im[432] = 32'hC3A94590; // 432 -0.882 -0.471 +assign wn_re[433] = 32'h8EBEF7FB; assign wn_im[433] = 32'hC45AE1D7; // 433 -0.885 -0.466 +assign wn_re[434] = 32'h8E61D32E; assign wn_im[434] = 32'hC50D1149; // 434 -0.888 -0.461 +assign wn_re[435] = 32'h8E05C6B7; assign wn_im[435] = 32'hC5BFD22E; // 435 -0.890 -0.455 +assign wn_re[436] = 32'h8DAAD37B; assign wn_im[436] = 32'hC67322CE; // 436 -0.893 -0.450 +assign wn_re[437] = 32'h8D50FA59; assign wn_im[437] = 32'hC727016D; // 437 -0.896 -0.444 +assign wn_re[438] = 32'h8CF83C30; assign wn_im[438] = 32'hC7DB6C50; // 438 -0.899 -0.439 +assign wn_re[439] = 32'h8CA099DA; assign wn_im[439] = 32'hC89061BA; // 439 -0.901 -0.433 +assign wn_re[440] = 32'h8C4A142F; assign wn_im[440] = 32'hC945DFEC; // 440 -0.904 -0.428 +assign wn_re[441] = 32'h8BF4AC05; assign wn_im[441] = 32'hC9FBE527; // 441 -0.907 -0.422 +assign wn_re[442] = 32'h8BA0622F; assign wn_im[442] = 32'hCAB26FA9; // 442 -0.909 -0.416 +assign wn_re[443] = 32'h8B4D377C; assign wn_im[443] = 32'hCB697DB0; // 443 -0.912 -0.411 +assign wn_re[444] = 32'h8AFB2CBB; assign wn_im[444] = 32'hCC210D79; // 444 -0.914 -0.405 +assign wn_re[445] = 32'h8AAA42B4; assign wn_im[445] = 32'hCCD91D3D; // 445 -0.917 -0.400 +assign wn_re[446] = 32'h8A5A7A31; assign wn_im[446] = 32'hCD91AB39; // 446 -0.919 -0.394 +assign wn_re[447] = 32'h8A0BD3F5; assign wn_im[447] = 32'hCE4AB5A2; // 447 -0.922 -0.388 +assign wn_re[448] = 32'h89BE50C3; assign wn_im[448] = 32'hCF043AB3; // 448 -0.924 -0.383 +assign wn_re[449] = 32'h8971F15A; assign wn_im[449] = 32'hCFBE389F; // 449 -0.926 -0.377 +assign wn_re[450] = 32'h8926B677; assign wn_im[450] = 32'hD078AD9E; // 450 -0.929 -0.371 +assign wn_re[451] = 32'h88DCA0D3; assign wn_im[451] = 32'hD13397E2; // 451 -0.931 -0.366 +assign wn_re[452] = 32'h8893B125; assign wn_im[452] = 32'hD1EEF59E; // 452 -0.933 -0.360 +assign wn_re[453] = 32'h884BE821; assign wn_im[453] = 32'hD2AAC504; // 453 -0.935 -0.354 +assign wn_re[454] = 32'h88054677; assign wn_im[454] = 32'hD3670446; // 454 -0.937 -0.348 +assign wn_re[455] = 32'h87BFCCD7; assign wn_im[455] = 32'hD423B191; // 455 -0.939 -0.343 +assign wn_re[456] = 32'h877B7BEC; assign wn_im[456] = 32'hD4E0CB15; // 456 -0.942 -0.337 +assign wn_re[457] = 32'h8738545E; assign wn_im[457] = 32'hD59E4EFF; // 457 -0.944 -0.331 +assign wn_re[458] = 32'h86F656D3; assign wn_im[458] = 32'hD65C3B7B; // 458 -0.946 -0.325 +assign wn_re[459] = 32'h86B583EE; assign wn_im[459] = 32'hD71A8EB5; // 459 -0.948 -0.320 +assign wn_re[460] = 32'h8675DC4F; assign wn_im[460] = 32'hD7D946D8; // 460 -0.950 -0.314 +assign wn_re[461] = 32'h86376092; assign wn_im[461] = 32'hD898620C; // 461 -0.951 -0.308 +assign wn_re[462] = 32'h85FA1153; assign wn_im[462] = 32'hD957DE7A; // 462 -0.953 -0.302 +assign wn_re[463] = 32'h85BDEF28; assign wn_im[463] = 32'hDA17BA4A; // 463 -0.955 -0.296 +assign wn_re[464] = 32'h8582FAA5; assign wn_im[464] = 32'hDAD7F3A2; // 464 -0.957 -0.290 +assign wn_re[465] = 32'h8549345C; assign wn_im[465] = 32'hDB9888A8; // 465 -0.959 -0.284 +assign wn_re[466] = 32'h85109CDD; assign wn_im[466] = 32'hDC597781; // 466 -0.960 -0.279 +assign wn_re[467] = 32'h84D934B1; assign wn_im[467] = 32'hDD1ABE51; // 467 -0.962 -0.273 +assign wn_re[468] = 32'h84A2FC62; assign wn_im[468] = 32'hDDDC5B3B; // 468 -0.964 -0.267 +assign wn_re[469] = 32'h846DF477; assign wn_im[469] = 32'hDE9E4C60; // 469 -0.965 -0.261 +assign wn_re[470] = 32'h843A1D70; assign wn_im[470] = 32'hDF608FE4; // 470 -0.967 -0.255 +assign wn_re[471] = 32'h840777D0; assign wn_im[471] = 32'hE02323E5; // 471 -0.969 -0.249 +assign wn_re[472] = 32'h83D60412; assign wn_im[472] = 32'hE0E60685; // 472 -0.970 -0.243 +assign wn_re[473] = 32'h83A5C2B0; assign wn_im[473] = 32'hE1A935E2; // 473 -0.972 -0.237 +assign wn_re[474] = 32'h8376B422; assign wn_im[474] = 32'hE26CB01B; // 474 -0.973 -0.231 +assign wn_re[475] = 32'h8348D8DC; assign wn_im[475] = 32'hE330734D; // 475 -0.974 -0.225 +assign wn_re[476] = 32'h831C314E; assign wn_im[476] = 32'hE3F47D96; // 476 -0.976 -0.219 +assign wn_re[477] = 32'h82F0BDE8; assign wn_im[477] = 32'hE4B8CD11; // 477 -0.977 -0.213 +assign wn_re[478] = 32'h82C67F14; assign wn_im[478] = 32'hE57D5FDA; // 478 -0.978 -0.207 +assign wn_re[479] = 32'h829D753A; assign wn_im[479] = 32'hE642340D; // 479 -0.980 -0.201 +assign wn_re[480] = 32'h8275A0C0; assign wn_im[480] = 32'hE70747C4; // 480 -0.981 -0.195 +assign wn_re[481] = 32'h824F0208; assign wn_im[481] = 32'hE7CC9917; // 481 -0.982 -0.189 +assign wn_re[482] = 32'h82299971; assign wn_im[482] = 32'hE8922622; // 482 -0.983 -0.183 +assign wn_re[483] = 32'h82056758; assign wn_im[483] = 32'hE957ECFB; // 483 -0.984 -0.177 +assign wn_re[484] = 32'h81E26C16; assign wn_im[484] = 32'hEA1DEBBB; // 484 -0.985 -0.171 +assign wn_re[485] = 32'h81C0A801; assign wn_im[485] = 32'hEAE4207A; // 485 -0.986 -0.165 +assign wn_re[486] = 32'h81A01B6D; assign wn_im[486] = 32'hEBAA894F; // 486 -0.987 -0.159 +assign wn_re[487] = 32'h8180C6A9; assign wn_im[487] = 32'hEC71244F; // 487 -0.988 -0.153 +assign wn_re[488] = 32'h8162AA04; assign wn_im[488] = 32'hED37EF91; // 488 -0.989 -0.147 +assign wn_re[489] = 32'h8145C5C7; assign wn_im[489] = 32'hEDFEE92B; // 489 -0.990 -0.141 +assign wn_re[490] = 32'h812A1A3A; assign wn_im[490] = 32'hEEC60F31; // 490 -0.991 -0.135 +assign wn_re[491] = 32'h810FA7A0; assign wn_im[491] = 32'hEF8D5FB8; // 491 -0.992 -0.128 +assign wn_re[492] = 32'h80F66E3C; assign wn_im[492] = 32'hF054D8D5; // 492 -0.992 -0.122 +assign wn_re[493] = 32'h80DE6E4C; assign wn_im[493] = 32'hF11C789A; // 493 -0.993 -0.116 +assign wn_re[494] = 32'h80C7A80A; assign wn_im[494] = 32'hF1E43D1C; // 494 -0.994 -0.110 +assign wn_re[495] = 32'h80B21BAF; assign wn_im[495] = 32'hF2AC246E; // 495 -0.995 -0.104 +assign wn_re[496] = 32'h809DC971; assign wn_im[496] = 32'hF3742CA2; // 496 -0.995 -0.098 +assign wn_re[497] = 32'h808AB180; assign wn_im[497] = 32'hF43C53CB; // 497 -0.996 -0.092 +assign wn_re[498] = 32'h8078D40D; assign wn_im[498] = 32'hF50497FB; // 498 -0.996 -0.086 +assign wn_re[499] = 32'h80683143; assign wn_im[499] = 32'hF5CCF743; // 499 -0.997 -0.080 +assign wn_re[500] = 32'h8058C94C; assign wn_im[500] = 32'hF6956FB7; // 500 -0.997 -0.074 +assign wn_re[501] = 32'h804A9C4D; assign wn_im[501] = 32'hF75DFF66; // 501 -0.998 -0.067 +assign wn_re[502] = 32'h803DAA6A; assign wn_im[502] = 32'hF826A462; // 502 -0.998 -0.061 +assign wn_re[503] = 32'h8031F3C2; assign wn_im[503] = 32'hF8EF5CBB; // 503 -0.998 -0.055 +assign wn_re[504] = 32'h80277872; assign wn_im[504] = 32'hF9B82684; // 504 -0.999 -0.049 +assign wn_re[505] = 32'h801E3895; assign wn_im[505] = 32'hFA80FFCB; // 505 -0.999 -0.043 +assign wn_re[506] = 32'h80163440; assign wn_im[506] = 32'hFB49E6A3; // 506 -0.999 -0.037 +assign wn_re[507] = 32'h800F6B88; assign wn_im[507] = 32'hFC12D91A; // 507 -1.000 -0.031 +assign wn_re[508] = 32'h8009DE7E; assign wn_im[508] = 32'hFCDBD541; // 508 -1.000 -0.025 +assign wn_re[509] = 32'h80058D2F; assign wn_im[509] = 32'hFDA4D929; // 509 -1.000 -0.018 +assign wn_re[510] = 32'h800277A6; assign wn_im[510] = 32'hFE6DE2E0; // 510 -1.000 -0.012 +assign wn_re[511] = 32'h80009DEA; assign wn_im[511] = 32'hFF36F078; // 511 -1.000 -0.006 +assign wn_re[512] = 32'h80000000; assign wn_im[512] = 32'h00000000; // 512 -1.000 -0.000 +assign wn_re[513] = 32'h80009DEA; assign wn_im[513] = 32'h00C90F88; // 513 -1.000 0.006 +assign wn_re[514] = 32'h800277A6; assign wn_im[514] = 32'h01921D20; // 514 -1.000 0.012 +assign wn_re[515] = 32'h80058D2F; assign wn_im[515] = 32'h025B26D7; // 515 -1.000 0.018 +assign wn_re[516] = 32'h8009DE7E; assign wn_im[516] = 32'h03242ABF; // 516 -1.000 0.025 +assign wn_re[517] = 32'h800F6B88; assign wn_im[517] = 32'h03ED26E6; // 517 -1.000 0.031 +assign wn_re[518] = 32'h80163440; assign wn_im[518] = 32'h04B6195D; // 518 -0.999 0.037 +assign wn_re[519] = 32'h801E3895; assign wn_im[519] = 32'h057F0035; // 519 -0.999 0.043 +assign wn_re[520] = 32'h80277872; assign wn_im[520] = 32'h0647D97C; // 520 -0.999 0.049 +assign wn_re[521] = 32'h8031F3C2; assign wn_im[521] = 32'h0710A345; // 521 -0.998 0.055 +assign wn_re[522] = 32'h803DAA6A; assign wn_im[522] = 32'h07D95B9E; // 522 -0.998 0.061 +assign wn_re[523] = 32'h804A9C4D; assign wn_im[523] = 32'h08A2009A; // 523 -0.998 0.067 +assign wn_re[524] = 32'h8058C94C; assign wn_im[524] = 32'h096A9049; // 524 -0.997 0.074 +assign wn_re[525] = 32'h80683143; assign wn_im[525] = 32'h0A3308BD; // 525 -0.997 0.080 +assign wn_re[526] = 32'h8078D40D; assign wn_im[526] = 32'h0AFB6805; // 526 -0.996 0.086 +assign wn_re[527] = 32'h808AB180; assign wn_im[527] = 32'h0BC3AC35; // 527 -0.996 0.092 +assign wn_re[528] = 32'h809DC971; assign wn_im[528] = 32'h0C8BD35E; // 528 -0.995 0.098 +assign wn_re[529] = 32'h80B21BAF; assign wn_im[529] = 32'h0D53DB92; // 529 -0.995 0.104 +assign wn_re[530] = 32'h80C7A80A; assign wn_im[530] = 32'h0E1BC2E4; // 530 -0.994 0.110 +assign wn_re[531] = 32'h80DE6E4C; assign wn_im[531] = 32'h0EE38766; // 531 -0.993 0.116 +assign wn_re[532] = 32'h80F66E3C; assign wn_im[532] = 32'h0FAB272B; // 532 -0.992 0.122 +assign wn_re[533] = 32'h810FA7A0; assign wn_im[533] = 32'h1072A048; // 533 -0.992 0.128 +assign wn_re[534] = 32'h812A1A3A; assign wn_im[534] = 32'h1139F0CF; // 534 -0.991 0.135 +assign wn_re[535] = 32'h8145C5C7; assign wn_im[535] = 32'h120116D5; // 535 -0.990 0.141 +assign wn_re[536] = 32'h8162AA04; assign wn_im[536] = 32'h12C8106F; // 536 -0.989 0.147 +assign wn_re[537] = 32'h8180C6A9; assign wn_im[537] = 32'h138EDBB1; // 537 -0.988 0.153 +assign wn_re[538] = 32'h81A01B6D; assign wn_im[538] = 32'h145576B1; // 538 -0.987 0.159 +assign wn_re[539] = 32'h81C0A801; assign wn_im[539] = 32'h151BDF86; // 539 -0.986 0.165 +assign wn_re[540] = 32'h81E26C16; assign wn_im[540] = 32'h15E21445; // 540 -0.985 0.171 +assign wn_re[541] = 32'h82056758; assign wn_im[541] = 32'h16A81305; // 541 -0.984 0.177 +assign wn_re[542] = 32'h82299971; assign wn_im[542] = 32'h176DD9DE; // 542 -0.983 0.183 +assign wn_re[543] = 32'h824F0208; assign wn_im[543] = 32'h183366E9; // 543 -0.982 0.189 +assign wn_re[544] = 32'h8275A0C0; assign wn_im[544] = 32'h18F8B83C; // 544 -0.981 0.195 +assign wn_re[545] = 32'h829D753A; assign wn_im[545] = 32'h19BDCBF3; // 545 -0.980 0.201 +assign wn_re[546] = 32'h82C67F14; assign wn_im[546] = 32'h1A82A026; // 546 -0.978 0.207 +assign wn_re[547] = 32'h82F0BDE8; assign wn_im[547] = 32'h1B4732EF; // 547 -0.977 0.213 +assign wn_re[548] = 32'h831C314E; assign wn_im[548] = 32'h1C0B826A; // 548 -0.976 0.219 +assign wn_re[549] = 32'h8348D8DC; assign wn_im[549] = 32'h1CCF8CB3; // 549 -0.974 0.225 +assign wn_re[550] = 32'h8376B422; assign wn_im[550] = 32'h1D934FE5; // 550 -0.973 0.231 +assign wn_re[551] = 32'h83A5C2B0; assign wn_im[551] = 32'h1E56CA1E; // 551 -0.972 0.237 +assign wn_re[552] = 32'h83D60412; assign wn_im[552] = 32'h1F19F97B; // 552 -0.970 0.243 +assign wn_re[553] = 32'h840777D0; assign wn_im[553] = 32'h1FDCDC1B; // 553 -0.969 0.249 +assign wn_re[554] = 32'h843A1D70; assign wn_im[554] = 32'h209F701C; // 554 -0.967 0.255 +assign wn_re[555] = 32'h846DF477; assign wn_im[555] = 32'h2161B3A0; // 555 -0.965 0.261 +assign wn_re[556] = 32'h84A2FC62; assign wn_im[556] = 32'h2223A4C5; // 556 -0.964 0.267 +assign wn_re[557] = 32'h84D934B1; assign wn_im[557] = 32'h22E541AF; // 557 -0.962 0.273 +assign wn_re[558] = 32'h85109CDD; assign wn_im[558] = 32'h23A6887F; // 558 -0.960 0.279 +assign wn_re[559] = 32'h8549345C; assign wn_im[559] = 32'h24677758; // 559 -0.959 0.284 +assign wn_re[560] = 32'h8582FAA5; assign wn_im[560] = 32'h25280C5E; // 560 -0.957 0.290 +assign wn_re[561] = 32'h85BDEF28; assign wn_im[561] = 32'h25E845B6; // 561 -0.955 0.296 +assign wn_re[562] = 32'h85FA1153; assign wn_im[562] = 32'h26A82186; // 562 -0.953 0.302 +assign wn_re[563] = 32'h86376092; assign wn_im[563] = 32'h27679DF4; // 563 -0.951 0.308 +assign wn_re[564] = 32'h8675DC4F; assign wn_im[564] = 32'h2826B928; // 564 -0.950 0.314 +assign wn_re[565] = 32'h86B583EE; assign wn_im[565] = 32'h28E5714B; // 565 -0.948 0.320 +assign wn_re[566] = 32'h86F656D3; assign wn_im[566] = 32'h29A3C485; // 566 -0.946 0.325 +assign wn_re[567] = 32'h8738545E; assign wn_im[567] = 32'h2A61B101; // 567 -0.944 0.331 +assign wn_re[568] = 32'h877B7BEC; assign wn_im[568] = 32'h2B1F34EB; // 568 -0.942 0.337 +assign wn_re[569] = 32'h87BFCCD7; assign wn_im[569] = 32'h2BDC4E6F; // 569 -0.939 0.343 +assign wn_re[570] = 32'h88054677; assign wn_im[570] = 32'h2C98FBBA; // 570 -0.937 0.348 +assign wn_re[571] = 32'h884BE821; assign wn_im[571] = 32'h2D553AFC; // 571 -0.935 0.354 +assign wn_re[572] = 32'h8893B125; assign wn_im[572] = 32'h2E110A62; // 572 -0.933 0.360 +assign wn_re[573] = 32'h88DCA0D3; assign wn_im[573] = 32'h2ECC681E; // 573 -0.931 0.366 +assign wn_re[574] = 32'h8926B677; assign wn_im[574] = 32'h2F875262; // 574 -0.929 0.371 +assign wn_re[575] = 32'h8971F15A; assign wn_im[575] = 32'h3041C761; // 575 -0.926 0.377 +assign wn_re[576] = 32'h89BE50C3; assign wn_im[576] = 32'h30FBC54D; // 576 -0.924 0.383 +assign wn_re[577] = 32'h8A0BD3F5; assign wn_im[577] = 32'h31B54A5E; // 577 -0.922 0.388 +assign wn_re[578] = 32'h8A5A7A31; assign wn_im[578] = 32'h326E54C7; // 578 -0.919 0.394 +assign wn_re[579] = 32'h8AAA42B4; assign wn_im[579] = 32'h3326E2C3; // 579 -0.917 0.400 +assign wn_re[580] = 32'h8AFB2CBB; assign wn_im[580] = 32'h33DEF287; // 580 -0.914 0.405 +assign wn_re[581] = 32'h8B4D377C; assign wn_im[581] = 32'h34968250; // 581 -0.912 0.411 +assign wn_re[582] = 32'h8BA0622F; assign wn_im[582] = 32'h354D9057; // 582 -0.909 0.416 +assign wn_re[583] = 32'h8BF4AC05; assign wn_im[583] = 32'h36041AD9; // 583 -0.907 0.422 +assign wn_re[584] = 32'h8C4A142F; assign wn_im[584] = 32'h36BA2014; // 584 -0.904 0.428 +assign wn_re[585] = 32'h8CA099DA; assign wn_im[585] = 32'h376F9E46; // 585 -0.901 0.433 +assign wn_re[586] = 32'h8CF83C30; assign wn_im[586] = 32'h382493B0; // 586 -0.899 0.439 +assign wn_re[587] = 32'h8D50FA59; assign wn_im[587] = 32'h38D8FE93; // 587 -0.896 0.444 +assign wn_re[588] = 32'h8DAAD37B; assign wn_im[588] = 32'h398CDD32; // 588 -0.893 0.450 +assign wn_re[589] = 32'h8E05C6B7; assign wn_im[589] = 32'h3A402DD2; // 589 -0.890 0.455 +assign wn_re[590] = 32'h8E61D32E; assign wn_im[590] = 32'h3AF2EEB7; // 590 -0.888 0.461 +assign wn_re[591] = 32'h8EBEF7FB; assign wn_im[591] = 32'h3BA51E29; // 591 -0.885 0.466 +assign wn_re[592] = 32'h8F1D343A; assign wn_im[592] = 32'h3C56BA70; // 592 -0.882 0.471 +assign wn_re[593] = 32'h8F7C8701; assign wn_im[593] = 32'h3D07C1D6; // 593 -0.879 0.477 +assign wn_re[594] = 32'h8FDCEF66; assign wn_im[594] = 32'h3DB832A6; // 594 -0.876 0.482 +assign wn_re[595] = 32'h903E6C7B; assign wn_im[595] = 32'h3E680B2C; // 595 -0.873 0.488 +assign wn_re[596] = 32'h90A0FD4E; assign wn_im[596] = 32'h3F1749B8; // 596 -0.870 0.493 +assign wn_re[597] = 32'h9104A0EE; assign wn_im[597] = 32'h3FC5EC98; // 597 -0.867 0.498 +assign wn_re[598] = 32'h91695663; assign wn_im[598] = 32'h4073F21D; // 598 -0.864 0.504 +assign wn_re[599] = 32'h91CF1CB6; assign wn_im[599] = 32'h4121589B; // 599 -0.861 0.509 +assign wn_re[600] = 32'h9235F2EC; assign wn_im[600] = 32'h41CE1E65; // 600 -0.858 0.514 +assign wn_re[601] = 32'h929DD806; assign wn_im[601] = 32'h427A41D0; // 601 -0.855 0.519 +assign wn_re[602] = 32'h9306CB04; assign wn_im[602] = 32'h4325C135; // 602 -0.851 0.525 +assign wn_re[603] = 32'h9370CAE4; assign wn_im[603] = 32'h43D09AED; // 603 -0.848 0.530 +assign wn_re[604] = 32'h93DBD6A0; assign wn_im[604] = 32'h447ACD50; // 604 -0.845 0.535 +assign wn_re[605] = 32'h9447ED2F; assign wn_im[605] = 32'h452456BD; // 605 -0.842 0.540 +assign wn_re[606] = 32'h94B50D87; assign wn_im[606] = 32'h45CD358F; // 606 -0.838 0.545 +assign wn_re[607] = 32'h9523369C; assign wn_im[607] = 32'h46756828; // 607 -0.835 0.550 +assign wn_re[608] = 32'h9592675C; assign wn_im[608] = 32'h471CECE7; // 608 -0.831 0.556 +assign wn_re[609] = 32'h96029EB6; assign wn_im[609] = 32'h47C3C22F; // 609 -0.828 0.561 +assign wn_re[610] = 32'h9673DB94; assign wn_im[610] = 32'h4869E665; // 610 -0.825 0.566 +assign wn_re[611] = 32'h96E61CE0; assign wn_im[611] = 32'h490F57EE; // 611 -0.821 0.571 +assign wn_re[612] = 32'h9759617F; assign wn_im[612] = 32'h49B41533; // 612 -0.818 0.576 +assign wn_re[613] = 32'h97CDA855; assign wn_im[613] = 32'h4A581C9E; // 613 -0.814 0.581 +assign wn_re[614] = 32'h9842F043; assign wn_im[614] = 32'h4AFB6C98; // 614 -0.810 0.586 +assign wn_re[615] = 32'h98B93828; assign wn_im[615] = 32'h4B9E0390; // 615 -0.807 0.591 +assign wn_re[616] = 32'h99307EE0; assign wn_im[616] = 32'h4C3FDFF4; // 616 -0.803 0.596 +assign wn_re[617] = 32'h99A8C345; assign wn_im[617] = 32'h4CE10034; // 617 -0.800 0.601 +assign wn_re[618] = 32'h9A22042D; assign wn_im[618] = 32'h4D8162C4; // 618 -0.796 0.606 +assign wn_re[619] = 32'h9A9C406E; assign wn_im[619] = 32'h4E210617; // 619 -0.792 0.610 +assign wn_re[620] = 32'h9B1776DA; assign wn_im[620] = 32'h4EBFE8A5; // 620 -0.788 0.615 +assign wn_re[621] = 32'h9B93A641; assign wn_im[621] = 32'h4F5E08E3; // 621 -0.785 0.620 +assign wn_re[622] = 32'h9C10CD70; assign wn_im[622] = 32'h4FFB654D; // 622 -0.781 0.625 +assign wn_re[623] = 32'h9C8EEB34; assign wn_im[623] = 32'h5097FC5E; // 623 -0.777 0.630 +assign wn_re[624] = 32'h9D0DFE54; assign wn_im[624] = 32'h5133CC94; // 624 -0.773 0.634 +assign wn_re[625] = 32'h9D8E0597; assign wn_im[625] = 32'h51CED46E; // 625 -0.769 0.639 +assign wn_re[626] = 32'h9E0EFFC1; assign wn_im[626] = 32'h5269126E; // 626 -0.765 0.644 +assign wn_re[627] = 32'h9E90EB94; assign wn_im[627] = 32'h53028518; // 627 -0.761 0.649 +assign wn_re[628] = 32'h9F13C7D0; assign wn_im[628] = 32'h539B2AF0; // 628 -0.757 0.653 +assign wn_re[629] = 32'h9F979331; assign wn_im[629] = 32'h5433027D; // 629 -0.753 0.658 +assign wn_re[630] = 32'hA01C4C73; assign wn_im[630] = 32'h54CA0A4B; // 630 -0.749 0.662 +assign wn_re[631] = 32'hA0A1F24D; assign wn_im[631] = 32'h556040E2; // 631 -0.745 0.667 +assign wn_re[632] = 32'hA1288376; assign wn_im[632] = 32'h55F5A4D2; // 632 -0.741 0.672 +assign wn_re[633] = 32'hA1AFFEA3; assign wn_im[633] = 32'h568A34A9; // 633 -0.737 0.676 +assign wn_re[634] = 32'hA2386284; assign wn_im[634] = 32'h571DEEFA; // 634 -0.733 0.681 +assign wn_re[635] = 32'hA2C1ADC9; assign wn_im[635] = 32'h57B0D256; // 635 -0.728 0.685 +assign wn_re[636] = 32'hA34BDF20; assign wn_im[636] = 32'h5842DD54; // 636 -0.724 0.690 +assign wn_re[637] = 32'hA3D6F534; assign wn_im[637] = 32'h58D40E8C; // 637 -0.720 0.694 +assign wn_re[638] = 32'hA462EEAC; assign wn_im[638] = 32'h59646498; // 638 -0.716 0.698 +assign wn_re[639] = 32'hA4EFCA31; assign wn_im[639] = 32'h59F3DE12; // 639 -0.711 0.703 +assign wn_re[640] = 32'hA57D8666; assign wn_im[640] = 32'h5A82799A; // 640 -0.707 0.707 +assign wn_re[641] = 32'hA60C21EE; assign wn_im[641] = 32'h5B1035CF; // 641 -0.703 0.711 +assign wn_re[642] = 32'hA69B9B68; assign wn_im[642] = 32'h5B9D1154; // 642 -0.698 0.716 +assign wn_re[643] = 32'hA72BF174; assign wn_im[643] = 32'h5C290ACC; // 643 -0.694 0.720 +assign wn_re[644] = 32'hA7BD22AC; assign wn_im[644] = 32'h5CB420E0; // 644 -0.690 0.724 +assign wn_re[645] = 32'hA84F2DAA; assign wn_im[645] = 32'h5D3E5237; // 645 -0.685 0.728 +assign wn_re[646] = 32'hA8E21106; assign wn_im[646] = 32'h5DC79D7C; // 646 -0.681 0.733 +assign wn_re[647] = 32'hA975CB57; assign wn_im[647] = 32'h5E50015D; // 647 -0.676 0.737 +assign wn_re[648] = 32'hAA0A5B2E; assign wn_im[648] = 32'h5ED77C8A; // 648 -0.672 0.741 +assign wn_re[649] = 32'hAA9FBF1E; assign wn_im[649] = 32'h5F5E0DB3; // 649 -0.667 0.745 +assign wn_re[650] = 32'hAB35F5B5; assign wn_im[650] = 32'h5FE3B38D; // 650 -0.662 0.749 +assign wn_re[651] = 32'hABCCFD83; assign wn_im[651] = 32'h60686CCF; // 651 -0.658 0.753 +assign wn_re[652] = 32'hAC64D510; assign wn_im[652] = 32'h60EC3830; // 652 -0.653 0.757 +assign wn_re[653] = 32'hACFD7AE8; assign wn_im[653] = 32'h616F146C; // 653 -0.649 0.761 +assign wn_re[654] = 32'hAD96ED92; assign wn_im[654] = 32'h61F1003F; // 654 -0.644 0.765 +assign wn_re[655] = 32'hAE312B92; assign wn_im[655] = 32'h6271FA69; // 655 -0.639 0.769 +assign wn_re[656] = 32'hAECC336C; assign wn_im[656] = 32'h62F201AC; // 656 -0.634 0.773 +assign wn_re[657] = 32'hAF6803A2; assign wn_im[657] = 32'h637114CC; // 657 -0.630 0.777 +assign wn_re[658] = 32'hB0049AB3; assign wn_im[658] = 32'h63EF3290; // 658 -0.625 0.781 +assign wn_re[659] = 32'hB0A1F71D; assign wn_im[659] = 32'h646C59BF; // 659 -0.620 0.785 +assign wn_re[660] = 32'hB140175B; assign wn_im[660] = 32'h64E88926; // 660 -0.615 0.788 +assign wn_re[661] = 32'hB1DEF9E9; assign wn_im[661] = 32'h6563BF92; // 661 -0.610 0.792 +assign wn_re[662] = 32'hB27E9D3C; assign wn_im[662] = 32'h65DDFBD3; // 662 -0.606 0.796 +assign wn_re[663] = 32'hB31EFFCC; assign wn_im[663] = 32'h66573CBB; // 663 -0.601 0.800 +assign wn_re[664] = 32'hB3C0200C; assign wn_im[664] = 32'h66CF8120; // 664 -0.596 0.803 +assign wn_re[665] = 32'hB461FC70; assign wn_im[665] = 32'h6746C7D8; // 665 -0.591 0.807 +assign wn_re[666] = 32'hB5049368; assign wn_im[666] = 32'h67BD0FBD; // 666 -0.586 0.810 +assign wn_re[667] = 32'hB5A7E362; assign wn_im[667] = 32'h683257AB; // 667 -0.581 0.814 +assign wn_re[668] = 32'hB64BEACD; assign wn_im[668] = 32'h68A69E81; // 668 -0.576 0.818 +assign wn_re[669] = 32'hB6F0A812; assign wn_im[669] = 32'h6919E320; // 669 -0.571 0.821 +assign wn_re[670] = 32'hB796199B; assign wn_im[670] = 32'h698C246C; // 670 -0.566 0.825 +assign wn_re[671] = 32'hB83C3DD1; assign wn_im[671] = 32'h69FD614A; // 671 -0.561 0.828 +assign wn_re[672] = 32'hB8E31319; assign wn_im[672] = 32'h6A6D98A4; // 672 -0.556 0.831 +assign wn_re[673] = 32'hB98A97D8; assign wn_im[673] = 32'h6ADCC964; // 673 -0.550 0.835 +assign wn_re[674] = 32'hBA32CA71; assign wn_im[674] = 32'h6B4AF279; // 674 -0.545 0.838 +assign wn_re[675] = 32'hBADBA943; assign wn_im[675] = 32'h6BB812D1; // 675 -0.540 0.842 +assign wn_re[676] = 32'hBB8532B0; assign wn_im[676] = 32'h6C242960; // 676 -0.535 0.845 +assign wn_re[677] = 32'hBC2F6513; assign wn_im[677] = 32'h6C8F351C; // 677 -0.530 0.848 +assign wn_re[678] = 32'hBCDA3ECB; assign wn_im[678] = 32'h6CF934FC; // 678 -0.525 0.851 +assign wn_re[679] = 32'hBD85BE30; assign wn_im[679] = 32'h6D6227FA; // 679 -0.519 0.855 +assign wn_re[680] = 32'hBE31E19B; assign wn_im[680] = 32'h6DCA0D14; // 680 -0.514 0.858 +assign wn_re[681] = 32'hBEDEA765; assign wn_im[681] = 32'h6E30E34A; // 681 -0.509 0.861 +assign wn_re[682] = 32'hBF8C0DE3; assign wn_im[682] = 32'h6E96A99D; // 682 -0.504 0.864 +assign wn_re[683] = 32'hC03A1368; assign wn_im[683] = 32'h6EFB5F12; // 683 -0.498 0.867 +assign wn_re[684] = 32'hC0E8B648; assign wn_im[684] = 32'h6F5F02B2; // 684 -0.493 0.870 +assign wn_re[685] = 32'hC197F4D4; assign wn_im[685] = 32'h6FC19385; // 685 -0.488 0.873 +assign wn_re[686] = 32'hC247CD5A; assign wn_im[686] = 32'h7023109A; // 686 -0.482 0.876 +assign wn_re[687] = 32'hC2F83E2A; assign wn_im[687] = 32'h708378FF; // 687 -0.477 0.879 +assign wn_re[688] = 32'hC3A94590; assign wn_im[688] = 32'h70E2CBC6; // 688 -0.471 0.882 +assign wn_re[689] = 32'hC45AE1D7; assign wn_im[689] = 32'h71410805; // 689 -0.466 0.885 +assign wn_re[690] = 32'hC50D1149; assign wn_im[690] = 32'h719E2CD2; // 690 -0.461 0.888 +assign wn_re[691] = 32'hC5BFD22E; assign wn_im[691] = 32'h71FA3949; // 691 -0.455 0.890 +assign wn_re[692] = 32'hC67322CE; assign wn_im[692] = 32'h72552C85; // 692 -0.450 0.893 +assign wn_re[693] = 32'hC727016D; assign wn_im[693] = 32'h72AF05A7; // 693 -0.444 0.896 +assign wn_re[694] = 32'hC7DB6C50; assign wn_im[694] = 32'h7307C3D0; // 694 -0.439 0.899 +assign wn_re[695] = 32'hC89061BA; assign wn_im[695] = 32'h735F6626; // 695 -0.433 0.901 +assign wn_re[696] = 32'hC945DFEC; assign wn_im[696] = 32'h73B5EBD1; // 696 -0.428 0.904 +assign wn_re[697] = 32'hC9FBE527; assign wn_im[697] = 32'h740B53FB; // 697 -0.422 0.907 +assign wn_re[698] = 32'hCAB26FA9; assign wn_im[698] = 32'h745F9DD1; // 698 -0.416 0.909 +assign wn_re[699] = 32'hCB697DB0; assign wn_im[699] = 32'h74B2C884; // 699 -0.411 0.912 +assign wn_re[700] = 32'hCC210D79; assign wn_im[700] = 32'h7504D345; // 700 -0.405 0.914 +assign wn_re[701] = 32'hCCD91D3D; assign wn_im[701] = 32'h7555BD4C; // 701 -0.400 0.917 +assign wn_re[702] = 32'hCD91AB39; assign wn_im[702] = 32'h75A585CF; // 702 -0.394 0.919 +assign wn_re[703] = 32'hCE4AB5A2; assign wn_im[703] = 32'h75F42C0B; // 703 -0.388 0.922 +assign wn_re[704] = 32'hCF043AB3; assign wn_im[704] = 32'h7641AF3D; // 704 -0.383 0.924 +assign wn_re[705] = 32'hCFBE389F; assign wn_im[705] = 32'h768E0EA6; // 705 -0.377 0.926 +assign wn_re[706] = 32'hD078AD9E; assign wn_im[706] = 32'h76D94989; // 706 -0.371 0.929 +assign wn_re[707] = 32'hD13397E2; assign wn_im[707] = 32'h77235F2D; // 707 -0.366 0.931 +assign wn_re[708] = 32'hD1EEF59E; assign wn_im[708] = 32'h776C4EDB; // 708 -0.360 0.933 +assign wn_re[709] = 32'hD2AAC504; assign wn_im[709] = 32'h77B417DF; // 709 -0.354 0.935 +assign wn_re[710] = 32'hD3670446; assign wn_im[710] = 32'h77FAB989; // 710 -0.348 0.937 +assign wn_re[711] = 32'hD423B191; assign wn_im[711] = 32'h78403329; // 711 -0.343 0.939 +assign wn_re[712] = 32'hD4E0CB15; assign wn_im[712] = 32'h78848414; // 712 -0.337 0.942 +assign wn_re[713] = 32'hD59E4EFF; assign wn_im[713] = 32'h78C7ABA2; // 713 -0.331 0.944 +assign wn_re[714] = 32'hD65C3B7B; assign wn_im[714] = 32'h7909A92D; // 714 -0.325 0.946 +assign wn_re[715] = 32'hD71A8EB5; assign wn_im[715] = 32'h794A7C12; // 715 -0.320 0.948 +assign wn_re[716] = 32'hD7D946D8; assign wn_im[716] = 32'h798A23B1; // 716 -0.314 0.950 +assign wn_re[717] = 32'hD898620C; assign wn_im[717] = 32'h79C89F6E; // 717 -0.308 0.951 +assign wn_re[718] = 32'hD957DE7A; assign wn_im[718] = 32'h7A05EEAD; // 718 -0.302 0.953 +assign wn_re[719] = 32'hDA17BA4A; assign wn_im[719] = 32'h7A4210D8; // 719 -0.296 0.955 +assign wn_re[720] = 32'hDAD7F3A2; assign wn_im[720] = 32'h7A7D055B; // 720 -0.290 0.957 +assign wn_re[721] = 32'hDB9888A8; assign wn_im[721] = 32'h7AB6CBA4; // 721 -0.284 0.959 +assign wn_re[722] = 32'hDC597781; assign wn_im[722] = 32'h7AEF6323; // 722 -0.279 0.960 +assign wn_re[723] = 32'hDD1ABE51; assign wn_im[723] = 32'h7B26CB4F; // 723 -0.273 0.962 +assign wn_re[724] = 32'hDDDC5B3B; assign wn_im[724] = 32'h7B5D039E; // 724 -0.267 0.964 +assign wn_re[725] = 32'hDE9E4C60; assign wn_im[725] = 32'h7B920B89; // 725 -0.261 0.965 +assign wn_re[726] = 32'hDF608FE4; assign wn_im[726] = 32'h7BC5E290; // 726 -0.255 0.967 +assign wn_re[727] = 32'hE02323E5; assign wn_im[727] = 32'h7BF88830; // 727 -0.249 0.969 +assign wn_re[728] = 32'hE0E60685; assign wn_im[728] = 32'h7C29FBEE; // 728 -0.243 0.970 +assign wn_re[729] = 32'hE1A935E2; assign wn_im[729] = 32'h7C5A3D50; // 729 -0.237 0.972 +assign wn_re[730] = 32'hE26CB01B; assign wn_im[730] = 32'h7C894BDE; // 730 -0.231 0.973 +assign wn_re[731] = 32'hE330734D; assign wn_im[731] = 32'h7CB72724; // 731 -0.225 0.974 +assign wn_re[732] = 32'hE3F47D96; assign wn_im[732] = 32'h7CE3CEB2; // 732 -0.219 0.976 +assign wn_re[733] = 32'hE4B8CD11; assign wn_im[733] = 32'h7D0F4218; // 733 -0.213 0.977 +assign wn_re[734] = 32'hE57D5FDA; assign wn_im[734] = 32'h7D3980EC; // 734 -0.207 0.978 +assign wn_re[735] = 32'hE642340D; assign wn_im[735] = 32'h7D628AC6; // 735 -0.201 0.980 +assign wn_re[736] = 32'hE70747C4; assign wn_im[736] = 32'h7D8A5F40; // 736 -0.195 0.981 +assign wn_re[737] = 32'hE7CC9917; assign wn_im[737] = 32'h7DB0FDF8; // 737 -0.189 0.982 +assign wn_re[738] = 32'hE8922622; assign wn_im[738] = 32'h7DD6668F; // 738 -0.183 0.983 +assign wn_re[739] = 32'hE957ECFB; assign wn_im[739] = 32'h7DFA98A8; // 739 -0.177 0.984 +assign wn_re[740] = 32'hEA1DEBBB; assign wn_im[740] = 32'h7E1D93EA; // 740 -0.171 0.985 +assign wn_re[741] = 32'hEAE4207A; assign wn_im[741] = 32'h7E3F57FF; // 741 -0.165 0.986 +assign wn_re[742] = 32'hEBAA894F; assign wn_im[742] = 32'h7E5FE493; // 742 -0.159 0.987 +assign wn_re[743] = 32'hEC71244F; assign wn_im[743] = 32'h7E7F3957; // 743 -0.153 0.988 +assign wn_re[744] = 32'hED37EF91; assign wn_im[744] = 32'h7E9D55FC; // 744 -0.147 0.989 +assign wn_re[745] = 32'hEDFEE92B; assign wn_im[745] = 32'h7EBA3A39; // 745 -0.141 0.990 +assign wn_re[746] = 32'hEEC60F31; assign wn_im[746] = 32'h7ED5E5C6; // 746 -0.135 0.991 +assign wn_re[747] = 32'hEF8D5FB8; assign wn_im[747] = 32'h7EF05860; // 747 -0.128 0.992 +assign wn_re[748] = 32'hF054D8D5; assign wn_im[748] = 32'h7F0991C4; // 748 -0.122 0.992 +assign wn_re[749] = 32'hF11C789A; assign wn_im[749] = 32'h7F2191B4; // 749 -0.116 0.993 +assign wn_re[750] = 32'hF1E43D1C; assign wn_im[750] = 32'h7F3857F6; // 750 -0.110 0.994 +assign wn_re[751] = 32'hF2AC246E; assign wn_im[751] = 32'h7F4DE451; // 751 -0.104 0.995 +assign wn_re[752] = 32'hF3742CA2; assign wn_im[752] = 32'h7F62368F; // 752 -0.098 0.995 +assign wn_re[753] = 32'hF43C53CB; assign wn_im[753] = 32'h7F754E80; // 753 -0.092 0.996 +assign wn_re[754] = 32'hF50497FB; assign wn_im[754] = 32'h7F872BF3; // 754 -0.086 0.996 +assign wn_re[755] = 32'hF5CCF743; assign wn_im[755] = 32'h7F97CEBD; // 755 -0.080 0.997 +assign wn_re[756] = 32'hF6956FB7; assign wn_im[756] = 32'h7FA736B4; // 756 -0.074 0.997 +assign wn_re[757] = 32'hF75DFF66; assign wn_im[757] = 32'h7FB563B3; // 757 -0.067 0.998 +assign wn_re[758] = 32'hF826A462; assign wn_im[758] = 32'h7FC25596; // 758 -0.061 0.998 +assign wn_re[759] = 32'hF8EF5CBB; assign wn_im[759] = 32'h7FCE0C3E; // 759 -0.055 0.998 +assign wn_re[760] = 32'hF9B82684; assign wn_im[760] = 32'h7FD8878E; // 760 -0.049 0.999 +assign wn_re[761] = 32'hFA80FFCB; assign wn_im[761] = 32'h7FE1C76B; // 761 -0.043 0.999 +assign wn_re[762] = 32'hFB49E6A3; assign wn_im[762] = 32'h7FE9CBC0; // 762 -0.037 0.999 +assign wn_re[763] = 32'hFC12D91A; assign wn_im[763] = 32'h7FF09478; // 763 -0.031 1.000 +assign wn_re[764] = 32'hFCDBD541; assign wn_im[764] = 32'h7FF62182; // 764 -0.025 1.000 +assign wn_re[765] = 32'hFDA4D929; assign wn_im[765] = 32'h7FFA72D1; // 765 -0.018 1.000 +assign wn_re[766] = 32'hFE6DE2E0; assign wn_im[766] = 32'h7FFD885A; // 766 -0.012 1.000 +assign wn_re[767] = 32'hFF36F078; assign wn_im[767] = 32'h7FFF6216; // 767 -0.006 1.000 +assign wn_re[768] = 32'h00000000; assign wn_im[768] = 32'h7FFFFFFF; // 768 -0.000 1.000 +assign wn_re[769] = 32'h00C90F88; assign wn_im[769] = 32'h7FFF6216; // 769 0.006 1.000 +assign wn_re[770] = 32'h01921D20; assign wn_im[770] = 32'h7FFD885A; // 770 0.012 1.000 +assign wn_re[771] = 32'h025B26D7; assign wn_im[771] = 32'h7FFA72D1; // 771 0.018 1.000 +assign wn_re[772] = 32'h03242ABF; assign wn_im[772] = 32'h7FF62182; // 772 0.025 1.000 +assign wn_re[773] = 32'h03ED26E6; assign wn_im[773] = 32'h7FF09478; // 773 0.031 1.000 +assign wn_re[774] = 32'h04B6195D; assign wn_im[774] = 32'h7FE9CBC0; // 774 0.037 0.999 +assign wn_re[775] = 32'h057F0035; assign wn_im[775] = 32'h7FE1C76B; // 775 0.043 0.999 +assign wn_re[776] = 32'h0647D97C; assign wn_im[776] = 32'h7FD8878E; // 776 0.049 0.999 +assign wn_re[777] = 32'h0710A345; assign wn_im[777] = 32'h7FCE0C3E; // 777 0.055 0.998 +assign wn_re[778] = 32'h07D95B9E; assign wn_im[778] = 32'h7FC25596; // 778 0.061 0.998 +assign wn_re[779] = 32'h08A2009A; assign wn_im[779] = 32'h7FB563B3; // 779 0.067 0.998 +assign wn_re[780] = 32'h096A9049; assign wn_im[780] = 32'h7FA736B4; // 780 0.074 0.997 +assign wn_re[781] = 32'h0A3308BD; assign wn_im[781] = 32'h7F97CEBD; // 781 0.080 0.997 +assign wn_re[782] = 32'h0AFB6805; assign wn_im[782] = 32'h7F872BF3; // 782 0.086 0.996 +assign wn_re[783] = 32'h0BC3AC35; assign wn_im[783] = 32'h7F754E80; // 783 0.092 0.996 +assign wn_re[784] = 32'h0C8BD35E; assign wn_im[784] = 32'h7F62368F; // 784 0.098 0.995 +assign wn_re[785] = 32'h0D53DB92; assign wn_im[785] = 32'h7F4DE451; // 785 0.104 0.995 +assign wn_re[786] = 32'h0E1BC2E4; assign wn_im[786] = 32'h7F3857F6; // 786 0.110 0.994 +assign wn_re[787] = 32'h0EE38766; assign wn_im[787] = 32'h7F2191B4; // 787 0.116 0.993 +assign wn_re[788] = 32'h0FAB272B; assign wn_im[788] = 32'h7F0991C4; // 788 0.122 0.992 +assign wn_re[789] = 32'h1072A048; assign wn_im[789] = 32'h7EF05860; // 789 0.128 0.992 +assign wn_re[790] = 32'h1139F0CF; assign wn_im[790] = 32'h7ED5E5C6; // 790 0.135 0.991 +assign wn_re[791] = 32'h120116D5; assign wn_im[791] = 32'h7EBA3A39; // 791 0.141 0.990 +assign wn_re[792] = 32'h12C8106F; assign wn_im[792] = 32'h7E9D55FC; // 792 0.147 0.989 +assign wn_re[793] = 32'h138EDBB1; assign wn_im[793] = 32'h7E7F3957; // 793 0.153 0.988 +assign wn_re[794] = 32'h145576B1; assign wn_im[794] = 32'h7E5FE493; // 794 0.159 0.987 +assign wn_re[795] = 32'h151BDF86; assign wn_im[795] = 32'h7E3F57FF; // 795 0.165 0.986 +assign wn_re[796] = 32'h15E21445; assign wn_im[796] = 32'h7E1D93EA; // 796 0.171 0.985 +assign wn_re[797] = 32'h16A81305; assign wn_im[797] = 32'h7DFA98A8; // 797 0.177 0.984 +assign wn_re[798] = 32'h176DD9DE; assign wn_im[798] = 32'h7DD6668F; // 798 0.183 0.983 +assign wn_re[799] = 32'h183366E9; assign wn_im[799] = 32'h7DB0FDF8; // 799 0.189 0.982 +assign wn_re[800] = 32'h18F8B83C; assign wn_im[800] = 32'h7D8A5F40; // 800 0.195 0.981 +assign wn_re[801] = 32'h19BDCBF3; assign wn_im[801] = 32'h7D628AC6; // 801 0.201 0.980 +assign wn_re[802] = 32'h1A82A026; assign wn_im[802] = 32'h7D3980EC; // 802 0.207 0.978 +assign wn_re[803] = 32'h1B4732EF; assign wn_im[803] = 32'h7D0F4218; // 803 0.213 0.977 +assign wn_re[804] = 32'h1C0B826A; assign wn_im[804] = 32'h7CE3CEB2; // 804 0.219 0.976 +assign wn_re[805] = 32'h1CCF8CB3; assign wn_im[805] = 32'h7CB72724; // 805 0.225 0.974 +assign wn_re[806] = 32'h1D934FE5; assign wn_im[806] = 32'h7C894BDE; // 806 0.231 0.973 +assign wn_re[807] = 32'h1E56CA1E; assign wn_im[807] = 32'h7C5A3D50; // 807 0.237 0.972 +assign wn_re[808] = 32'h1F19F97B; assign wn_im[808] = 32'h7C29FBEE; // 808 0.243 0.970 +assign wn_re[809] = 32'h1FDCDC1B; assign wn_im[809] = 32'h7BF88830; // 809 0.249 0.969 +assign wn_re[810] = 32'h209F701C; assign wn_im[810] = 32'h7BC5E290; // 810 0.255 0.967 +assign wn_re[811] = 32'h2161B3A0; assign wn_im[811] = 32'h7B920B89; // 811 0.261 0.965 +assign wn_re[812] = 32'h2223A4C5; assign wn_im[812] = 32'h7B5D039E; // 812 0.267 0.964 +assign wn_re[813] = 32'h22E541AF; assign wn_im[813] = 32'h7B26CB4F; // 813 0.273 0.962 +assign wn_re[814] = 32'h23A6887F; assign wn_im[814] = 32'h7AEF6323; // 814 0.279 0.960 +assign wn_re[815] = 32'h24677758; assign wn_im[815] = 32'h7AB6CBA4; // 815 0.284 0.959 +assign wn_re[816] = 32'h25280C5E; assign wn_im[816] = 32'h7A7D055B; // 816 0.290 0.957 +assign wn_re[817] = 32'h25E845B6; assign wn_im[817] = 32'h7A4210D8; // 817 0.296 0.955 +assign wn_re[818] = 32'h26A82186; assign wn_im[818] = 32'h7A05EEAD; // 818 0.302 0.953 +assign wn_re[819] = 32'h27679DF4; assign wn_im[819] = 32'h79C89F6E; // 819 0.308 0.951 +assign wn_re[820] = 32'h2826B928; assign wn_im[820] = 32'h798A23B1; // 820 0.314 0.950 +assign wn_re[821] = 32'h28E5714B; assign wn_im[821] = 32'h794A7C12; // 821 0.320 0.948 +assign wn_re[822] = 32'h29A3C485; assign wn_im[822] = 32'h7909A92D; // 822 0.325 0.946 +assign wn_re[823] = 32'h2A61B101; assign wn_im[823] = 32'h78C7ABA2; // 823 0.331 0.944 +assign wn_re[824] = 32'h2B1F34EB; assign wn_im[824] = 32'h78848414; // 824 0.337 0.942 +assign wn_re[825] = 32'h2BDC4E6F; assign wn_im[825] = 32'h78403329; // 825 0.343 0.939 +assign wn_re[826] = 32'h2C98FBBA; assign wn_im[826] = 32'h77FAB989; // 826 0.348 0.937 +assign wn_re[827] = 32'h2D553AFC; assign wn_im[827] = 32'h77B417DF; // 827 0.354 0.935 +assign wn_re[828] = 32'h2E110A62; assign wn_im[828] = 32'h776C4EDB; // 828 0.360 0.933 +assign wn_re[829] = 32'h2ECC681E; assign wn_im[829] = 32'h77235F2D; // 829 0.366 0.931 +assign wn_re[830] = 32'h2F875262; assign wn_im[830] = 32'h76D94989; // 830 0.371 0.929 +assign wn_re[831] = 32'h3041C761; assign wn_im[831] = 32'h768E0EA6; // 831 0.377 0.926 +assign wn_re[832] = 32'h30FBC54D; assign wn_im[832] = 32'h7641AF3D; // 832 0.383 0.924 +assign wn_re[833] = 32'h31B54A5E; assign wn_im[833] = 32'h75F42C0B; // 833 0.388 0.922 +assign wn_re[834] = 32'h326E54C7; assign wn_im[834] = 32'h75A585CF; // 834 0.394 0.919 +assign wn_re[835] = 32'h3326E2C3; assign wn_im[835] = 32'h7555BD4C; // 835 0.400 0.917 +assign wn_re[836] = 32'h33DEF287; assign wn_im[836] = 32'h7504D345; // 836 0.405 0.914 +assign wn_re[837] = 32'h34968250; assign wn_im[837] = 32'h74B2C884; // 837 0.411 0.912 +assign wn_re[838] = 32'h354D9057; assign wn_im[838] = 32'h745F9DD1; // 838 0.416 0.909 +assign wn_re[839] = 32'h36041AD9; assign wn_im[839] = 32'h740B53FB; // 839 0.422 0.907 +assign wn_re[840] = 32'h36BA2014; assign wn_im[840] = 32'h73B5EBD1; // 840 0.428 0.904 +assign wn_re[841] = 32'h376F9E46; assign wn_im[841] = 32'h735F6626; // 841 0.433 0.901 +assign wn_re[842] = 32'h382493B0; assign wn_im[842] = 32'h7307C3D0; // 842 0.439 0.899 +assign wn_re[843] = 32'h38D8FE93; assign wn_im[843] = 32'h72AF05A7; // 843 0.444 0.896 +assign wn_re[844] = 32'h398CDD32; assign wn_im[844] = 32'h72552C85; // 844 0.450 0.893 +assign wn_re[845] = 32'h3A402DD2; assign wn_im[845] = 32'h71FA3949; // 845 0.455 0.890 +assign wn_re[846] = 32'h3AF2EEB7; assign wn_im[846] = 32'h719E2CD2; // 846 0.461 0.888 +assign wn_re[847] = 32'h3BA51E29; assign wn_im[847] = 32'h71410805; // 847 0.466 0.885 +assign wn_re[848] = 32'h3C56BA70; assign wn_im[848] = 32'h70E2CBC6; // 848 0.471 0.882 +assign wn_re[849] = 32'h3D07C1D6; assign wn_im[849] = 32'h708378FF; // 849 0.477 0.879 +assign wn_re[850] = 32'h3DB832A6; assign wn_im[850] = 32'h7023109A; // 850 0.482 0.876 +assign wn_re[851] = 32'h3E680B2C; assign wn_im[851] = 32'h6FC19385; // 851 0.488 0.873 +assign wn_re[852] = 32'h3F1749B8; assign wn_im[852] = 32'h6F5F02B2; // 852 0.493 0.870 +assign wn_re[853] = 32'h3FC5EC98; assign wn_im[853] = 32'h6EFB5F12; // 853 0.498 0.867 +assign wn_re[854] = 32'h4073F21D; assign wn_im[854] = 32'h6E96A99D; // 854 0.504 0.864 +assign wn_re[855] = 32'h4121589B; assign wn_im[855] = 32'h6E30E34A; // 855 0.509 0.861 +assign wn_re[856] = 32'h41CE1E65; assign wn_im[856] = 32'h6DCA0D14; // 856 0.514 0.858 +assign wn_re[857] = 32'h427A41D0; assign wn_im[857] = 32'h6D6227FA; // 857 0.519 0.855 +assign wn_re[858] = 32'h4325C135; assign wn_im[858] = 32'h6CF934FC; // 858 0.525 0.851 +assign wn_re[859] = 32'h43D09AED; assign wn_im[859] = 32'h6C8F351C; // 859 0.530 0.848 +assign wn_re[860] = 32'h447ACD50; assign wn_im[860] = 32'h6C242960; // 860 0.535 0.845 +assign wn_re[861] = 32'h452456BD; assign wn_im[861] = 32'h6BB812D1; // 861 0.540 0.842 +assign wn_re[862] = 32'h45CD358F; assign wn_im[862] = 32'h6B4AF279; // 862 0.545 0.838 +assign wn_re[863] = 32'h46756828; assign wn_im[863] = 32'h6ADCC964; // 863 0.550 0.835 +assign wn_re[864] = 32'h471CECE7; assign wn_im[864] = 32'h6A6D98A4; // 864 0.556 0.831 +assign wn_re[865] = 32'h47C3C22F; assign wn_im[865] = 32'h69FD614A; // 865 0.561 0.828 +assign wn_re[866] = 32'h4869E665; assign wn_im[866] = 32'h698C246C; // 866 0.566 0.825 +assign wn_re[867] = 32'h490F57EE; assign wn_im[867] = 32'h6919E320; // 867 0.571 0.821 +assign wn_re[868] = 32'h49B41533; assign wn_im[868] = 32'h68A69E81; // 868 0.576 0.818 +assign wn_re[869] = 32'h4A581C9E; assign wn_im[869] = 32'h683257AB; // 869 0.581 0.814 +assign wn_re[870] = 32'h4AFB6C98; assign wn_im[870] = 32'h67BD0FBD; // 870 0.586 0.810 +assign wn_re[871] = 32'h4B9E0390; assign wn_im[871] = 32'h6746C7D8; // 871 0.591 0.807 +assign wn_re[872] = 32'h4C3FDFF4; assign wn_im[872] = 32'h66CF8120; // 872 0.596 0.803 +assign wn_re[873] = 32'h4CE10034; assign wn_im[873] = 32'h66573CBB; // 873 0.601 0.800 +assign wn_re[874] = 32'h4D8162C4; assign wn_im[874] = 32'h65DDFBD3; // 874 0.606 0.796 +assign wn_re[875] = 32'h4E210617; assign wn_im[875] = 32'h6563BF92; // 875 0.610 0.792 +assign wn_re[876] = 32'h4EBFE8A5; assign wn_im[876] = 32'h64E88926; // 876 0.615 0.788 +assign wn_re[877] = 32'h4F5E08E3; assign wn_im[877] = 32'h646C59BF; // 877 0.620 0.785 +assign wn_re[878] = 32'h4FFB654D; assign wn_im[878] = 32'h63EF3290; // 878 0.625 0.781 +assign wn_re[879] = 32'h5097FC5E; assign wn_im[879] = 32'h637114CC; // 879 0.630 0.777 +assign wn_re[880] = 32'h5133CC94; assign wn_im[880] = 32'h62F201AC; // 880 0.634 0.773 +assign wn_re[881] = 32'h51CED46E; assign wn_im[881] = 32'h6271FA69; // 881 0.639 0.769 +assign wn_re[882] = 32'h5269126E; assign wn_im[882] = 32'h61F1003F; // 882 0.644 0.765 +assign wn_re[883] = 32'h53028518; assign wn_im[883] = 32'h616F146C; // 883 0.649 0.761 +assign wn_re[884] = 32'h539B2AF0; assign wn_im[884] = 32'h60EC3830; // 884 0.653 0.757 +assign wn_re[885] = 32'h5433027D; assign wn_im[885] = 32'h60686CCF; // 885 0.658 0.753 +assign wn_re[886] = 32'h54CA0A4B; assign wn_im[886] = 32'h5FE3B38D; // 886 0.662 0.749 +assign wn_re[887] = 32'h556040E2; assign wn_im[887] = 32'h5F5E0DB3; // 887 0.667 0.745 +assign wn_re[888] = 32'h55F5A4D2; assign wn_im[888] = 32'h5ED77C8A; // 888 0.672 0.741 +assign wn_re[889] = 32'h568A34A9; assign wn_im[889] = 32'h5E50015D; // 889 0.676 0.737 +assign wn_re[890] = 32'h571DEEFA; assign wn_im[890] = 32'h5DC79D7C; // 890 0.681 0.733 +assign wn_re[891] = 32'h57B0D256; assign wn_im[891] = 32'h5D3E5237; // 891 0.685 0.728 +assign wn_re[892] = 32'h5842DD54; assign wn_im[892] = 32'h5CB420E0; // 892 0.690 0.724 +assign wn_re[893] = 32'h58D40E8C; assign wn_im[893] = 32'h5C290ACC; // 893 0.694 0.720 +assign wn_re[894] = 32'h59646498; assign wn_im[894] = 32'h5B9D1154; // 894 0.698 0.716 +assign wn_re[895] = 32'h59F3DE12; assign wn_im[895] = 32'h5B1035CF; // 895 0.703 0.711 +assign wn_re[896] = 32'h5A82799A; assign wn_im[896] = 32'h5A82799A; // 896 0.707 0.707 +assign wn_re[897] = 32'h5B1035CF; assign wn_im[897] = 32'h59F3DE12; // 897 0.711 0.703 +assign wn_re[898] = 32'h5B9D1154; assign wn_im[898] = 32'h59646498; // 898 0.716 0.698 +assign wn_re[899] = 32'h5C290ACC; assign wn_im[899] = 32'h58D40E8C; // 899 0.720 0.694 +assign wn_re[900] = 32'h5CB420E0; assign wn_im[900] = 32'h5842DD54; // 900 0.724 0.690 +assign wn_re[901] = 32'h5D3E5237; assign wn_im[901] = 32'h57B0D256; // 901 0.728 0.685 +assign wn_re[902] = 32'h5DC79D7C; assign wn_im[902] = 32'h571DEEFA; // 902 0.733 0.681 +assign wn_re[903] = 32'h5E50015D; assign wn_im[903] = 32'h568A34A9; // 903 0.737 0.676 +assign wn_re[904] = 32'h5ED77C8A; assign wn_im[904] = 32'h55F5A4D2; // 904 0.741 0.672 +assign wn_re[905] = 32'h5F5E0DB3; assign wn_im[905] = 32'h556040E2; // 905 0.745 0.667 +assign wn_re[906] = 32'h5FE3B38D; assign wn_im[906] = 32'h54CA0A4B; // 906 0.749 0.662 +assign wn_re[907] = 32'h60686CCF; assign wn_im[907] = 32'h5433027D; // 907 0.753 0.658 +assign wn_re[908] = 32'h60EC3830; assign wn_im[908] = 32'h539B2AF0; // 908 0.757 0.653 +assign wn_re[909] = 32'h616F146C; assign wn_im[909] = 32'h53028518; // 909 0.761 0.649 +assign wn_re[910] = 32'h61F1003F; assign wn_im[910] = 32'h5269126E; // 910 0.765 0.644 +assign wn_re[911] = 32'h6271FA69; assign wn_im[911] = 32'h51CED46E; // 911 0.769 0.639 +assign wn_re[912] = 32'h62F201AC; assign wn_im[912] = 32'h5133CC94; // 912 0.773 0.634 +assign wn_re[913] = 32'h637114CC; assign wn_im[913] = 32'h5097FC5E; // 913 0.777 0.630 +assign wn_re[914] = 32'h63EF3290; assign wn_im[914] = 32'h4FFB654D; // 914 0.781 0.625 +assign wn_re[915] = 32'h646C59BF; assign wn_im[915] = 32'h4F5E08E3; // 915 0.785 0.620 +assign wn_re[916] = 32'h64E88926; assign wn_im[916] = 32'h4EBFE8A5; // 916 0.788 0.615 +assign wn_re[917] = 32'h6563BF92; assign wn_im[917] = 32'h4E210617; // 917 0.792 0.610 +assign wn_re[918] = 32'h65DDFBD3; assign wn_im[918] = 32'h4D8162C4; // 918 0.796 0.606 +assign wn_re[919] = 32'h66573CBB; assign wn_im[919] = 32'h4CE10034; // 919 0.800 0.601 +assign wn_re[920] = 32'h66CF8120; assign wn_im[920] = 32'h4C3FDFF4; // 920 0.803 0.596 +assign wn_re[921] = 32'h6746C7D8; assign wn_im[921] = 32'h4B9E0390; // 921 0.807 0.591 +assign wn_re[922] = 32'h67BD0FBD; assign wn_im[922] = 32'h4AFB6C98; // 922 0.810 0.586 +assign wn_re[923] = 32'h683257AB; assign wn_im[923] = 32'h4A581C9E; // 923 0.814 0.581 +assign wn_re[924] = 32'h68A69E81; assign wn_im[924] = 32'h49B41533; // 924 0.818 0.576 +assign wn_re[925] = 32'h6919E320; assign wn_im[925] = 32'h490F57EE; // 925 0.821 0.571 +assign wn_re[926] = 32'h698C246C; assign wn_im[926] = 32'h4869E665; // 926 0.825 0.566 +assign wn_re[927] = 32'h69FD614A; assign wn_im[927] = 32'h47C3C22F; // 927 0.828 0.561 +assign wn_re[928] = 32'h6A6D98A4; assign wn_im[928] = 32'h471CECE7; // 928 0.831 0.556 +assign wn_re[929] = 32'h6ADCC964; assign wn_im[929] = 32'h46756828; // 929 0.835 0.550 +assign wn_re[930] = 32'h6B4AF279; assign wn_im[930] = 32'h45CD358F; // 930 0.838 0.545 +assign wn_re[931] = 32'h6BB812D1; assign wn_im[931] = 32'h452456BD; // 931 0.842 0.540 +assign wn_re[932] = 32'h6C242960; assign wn_im[932] = 32'h447ACD50; // 932 0.845 0.535 +assign wn_re[933] = 32'h6C8F351C; assign wn_im[933] = 32'h43D09AED; // 933 0.848 0.530 +assign wn_re[934] = 32'h6CF934FC; assign wn_im[934] = 32'h4325C135; // 934 0.851 0.525 +assign wn_re[935] = 32'h6D6227FA; assign wn_im[935] = 32'h427A41D0; // 935 0.855 0.519 +assign wn_re[936] = 32'h6DCA0D14; assign wn_im[936] = 32'h41CE1E65; // 936 0.858 0.514 +assign wn_re[937] = 32'h6E30E34A; assign wn_im[937] = 32'h4121589B; // 937 0.861 0.509 +assign wn_re[938] = 32'h6E96A99D; assign wn_im[938] = 32'h4073F21D; // 938 0.864 0.504 +assign wn_re[939] = 32'h6EFB5F12; assign wn_im[939] = 32'h3FC5EC98; // 939 0.867 0.498 +assign wn_re[940] = 32'h6F5F02B2; assign wn_im[940] = 32'h3F1749B8; // 940 0.870 0.493 +assign wn_re[941] = 32'h6FC19385; assign wn_im[941] = 32'h3E680B2C; // 941 0.873 0.488 +assign wn_re[942] = 32'h7023109A; assign wn_im[942] = 32'h3DB832A6; // 942 0.876 0.482 +assign wn_re[943] = 32'h708378FF; assign wn_im[943] = 32'h3D07C1D6; // 943 0.879 0.477 +assign wn_re[944] = 32'h70E2CBC6; assign wn_im[944] = 32'h3C56BA70; // 944 0.882 0.471 +assign wn_re[945] = 32'h71410805; assign wn_im[945] = 32'h3BA51E29; // 945 0.885 0.466 +assign wn_re[946] = 32'h719E2CD2; assign wn_im[946] = 32'h3AF2EEB7; // 946 0.888 0.461 +assign wn_re[947] = 32'h71FA3949; assign wn_im[947] = 32'h3A402DD2; // 947 0.890 0.455 +assign wn_re[948] = 32'h72552C85; assign wn_im[948] = 32'h398CDD32; // 948 0.893 0.450 +assign wn_re[949] = 32'h72AF05A7; assign wn_im[949] = 32'h38D8FE93; // 949 0.896 0.444 +assign wn_re[950] = 32'h7307C3D0; assign wn_im[950] = 32'h382493B0; // 950 0.899 0.439 +assign wn_re[951] = 32'h735F6626; assign wn_im[951] = 32'h376F9E46; // 951 0.901 0.433 +assign wn_re[952] = 32'h73B5EBD1; assign wn_im[952] = 32'h36BA2014; // 952 0.904 0.428 +assign wn_re[953] = 32'h740B53FB; assign wn_im[953] = 32'h36041AD9; // 953 0.907 0.422 +assign wn_re[954] = 32'h745F9DD1; assign wn_im[954] = 32'h354D9057; // 954 0.909 0.416 +assign wn_re[955] = 32'h74B2C884; assign wn_im[955] = 32'h34968250; // 955 0.912 0.411 +assign wn_re[956] = 32'h7504D345; assign wn_im[956] = 32'h33DEF287; // 956 0.914 0.405 +assign wn_re[957] = 32'h7555BD4C; assign wn_im[957] = 32'h3326E2C3; // 957 0.917 0.400 +assign wn_re[958] = 32'h75A585CF; assign wn_im[958] = 32'h326E54C7; // 958 0.919 0.394 +assign wn_re[959] = 32'h75F42C0B; assign wn_im[959] = 32'h31B54A5E; // 959 0.922 0.388 +assign wn_re[960] = 32'h7641AF3D; assign wn_im[960] = 32'h30FBC54D; // 960 0.924 0.383 +assign wn_re[961] = 32'h768E0EA6; assign wn_im[961] = 32'h3041C761; // 961 0.926 0.377 +assign wn_re[962] = 32'h76D94989; assign wn_im[962] = 32'h2F875262; // 962 0.929 0.371 +assign wn_re[963] = 32'h77235F2D; assign wn_im[963] = 32'h2ECC681E; // 963 0.931 0.366 +assign wn_re[964] = 32'h776C4EDB; assign wn_im[964] = 32'h2E110A62; // 964 0.933 0.360 +assign wn_re[965] = 32'h77B417DF; assign wn_im[965] = 32'h2D553AFC; // 965 0.935 0.354 +assign wn_re[966] = 32'h77FAB989; assign wn_im[966] = 32'h2C98FBBA; // 966 0.937 0.348 +assign wn_re[967] = 32'h78403329; assign wn_im[967] = 32'h2BDC4E6F; // 967 0.939 0.343 +assign wn_re[968] = 32'h78848414; assign wn_im[968] = 32'h2B1F34EB; // 968 0.942 0.337 +assign wn_re[969] = 32'h78C7ABA2; assign wn_im[969] = 32'h2A61B101; // 969 0.944 0.331 +assign wn_re[970] = 32'h7909A92D; assign wn_im[970] = 32'h29A3C485; // 970 0.946 0.325 +assign wn_re[971] = 32'h794A7C12; assign wn_im[971] = 32'h28E5714B; // 971 0.948 0.320 +assign wn_re[972] = 32'h798A23B1; assign wn_im[972] = 32'h2826B928; // 972 0.950 0.314 +assign wn_re[973] = 32'h79C89F6E; assign wn_im[973] = 32'h27679DF4; // 973 0.951 0.308 +assign wn_re[974] = 32'h7A05EEAD; assign wn_im[974] = 32'h26A82186; // 974 0.953 0.302 +assign wn_re[975] = 32'h7A4210D8; assign wn_im[975] = 32'h25E845B6; // 975 0.955 0.296 +assign wn_re[976] = 32'h7A7D055B; assign wn_im[976] = 32'h25280C5E; // 976 0.957 0.290 +assign wn_re[977] = 32'h7AB6CBA4; assign wn_im[977] = 32'h24677758; // 977 0.959 0.284 +assign wn_re[978] = 32'h7AEF6323; assign wn_im[978] = 32'h23A6887F; // 978 0.960 0.279 +assign wn_re[979] = 32'h7B26CB4F; assign wn_im[979] = 32'h22E541AF; // 979 0.962 0.273 +assign wn_re[980] = 32'h7B5D039E; assign wn_im[980] = 32'h2223A4C5; // 980 0.964 0.267 +assign wn_re[981] = 32'h7B920B89; assign wn_im[981] = 32'h2161B3A0; // 981 0.965 0.261 +assign wn_re[982] = 32'h7BC5E290; assign wn_im[982] = 32'h209F701C; // 982 0.967 0.255 +assign wn_re[983] = 32'h7BF88830; assign wn_im[983] = 32'h1FDCDC1B; // 983 0.969 0.249 +assign wn_re[984] = 32'h7C29FBEE; assign wn_im[984] = 32'h1F19F97B; // 984 0.970 0.243 +assign wn_re[985] = 32'h7C5A3D50; assign wn_im[985] = 32'h1E56CA1E; // 985 0.972 0.237 +assign wn_re[986] = 32'h7C894BDE; assign wn_im[986] = 32'h1D934FE5; // 986 0.973 0.231 +assign wn_re[987] = 32'h7CB72724; assign wn_im[987] = 32'h1CCF8CB3; // 987 0.974 0.225 +assign wn_re[988] = 32'h7CE3CEB2; assign wn_im[988] = 32'h1C0B826A; // 988 0.976 0.219 +assign wn_re[989] = 32'h7D0F4218; assign wn_im[989] = 32'h1B4732EF; // 989 0.977 0.213 +assign wn_re[990] = 32'h7D3980EC; assign wn_im[990] = 32'h1A82A026; // 990 0.978 0.207 +assign wn_re[991] = 32'h7D628AC6; assign wn_im[991] = 32'h19BDCBF3; // 991 0.980 0.201 +assign wn_re[992] = 32'h7D8A5F40; assign wn_im[992] = 32'h18F8B83C; // 992 0.981 0.195 +assign wn_re[993] = 32'h7DB0FDF8; assign wn_im[993] = 32'h183366E9; // 993 0.982 0.189 +assign wn_re[994] = 32'h7DD6668F; assign wn_im[994] = 32'h176DD9DE; // 994 0.983 0.183 +assign wn_re[995] = 32'h7DFA98A8; assign wn_im[995] = 32'h16A81305; // 995 0.984 0.177 +assign wn_re[996] = 32'h7E1D93EA; assign wn_im[996] = 32'h15E21445; // 996 0.985 0.171 +assign wn_re[997] = 32'h7E3F57FF; assign wn_im[997] = 32'h151BDF86; // 997 0.986 0.165 +assign wn_re[998] = 32'h7E5FE493; assign wn_im[998] = 32'h145576B1; // 998 0.987 0.159 +assign wn_re[999] = 32'h7E7F3957; assign wn_im[999] = 32'h138EDBB1; // 999 0.988 0.153 +assign wn_re[1000] = 32'h7E9D55FC; assign wn_im[1000] = 32'h12C8106F; // 1000 0.989 0.147 +assign wn_re[1001] = 32'h7EBA3A39; assign wn_im[1001] = 32'h120116D5; // 1001 0.990 0.141 +assign wn_re[1002] = 32'h7ED5E5C6; assign wn_im[1002] = 32'h1139F0CF; // 1002 0.991 0.135 +assign wn_re[1003] = 32'h7EF05860; assign wn_im[1003] = 32'h1072A048; // 1003 0.992 0.128 +assign wn_re[1004] = 32'h7F0991C4; assign wn_im[1004] = 32'h0FAB272B; // 1004 0.992 0.122 +assign wn_re[1005] = 32'h7F2191B4; assign wn_im[1005] = 32'h0EE38766; // 1005 0.993 0.116 +assign wn_re[1006] = 32'h7F3857F6; assign wn_im[1006] = 32'h0E1BC2E4; // 1006 0.994 0.110 +assign wn_re[1007] = 32'h7F4DE451; assign wn_im[1007] = 32'h0D53DB92; // 1007 0.995 0.104 +assign wn_re[1008] = 32'h7F62368F; assign wn_im[1008] = 32'h0C8BD35E; // 1008 0.995 0.098 +assign wn_re[1009] = 32'h7F754E80; assign wn_im[1009] = 32'h0BC3AC35; // 1009 0.996 0.092 +assign wn_re[1010] = 32'h7F872BF3; assign wn_im[1010] = 32'h0AFB6805; // 1010 0.996 0.086 +assign wn_re[1011] = 32'h7F97CEBD; assign wn_im[1011] = 32'h0A3308BD; // 1011 0.997 0.080 +assign wn_re[1012] = 32'h7FA736B4; assign wn_im[1012] = 32'h096A9049; // 1012 0.997 0.074 +assign wn_re[1013] = 32'h7FB563B3; assign wn_im[1013] = 32'h08A2009A; // 1013 0.998 0.067 +assign wn_re[1014] = 32'h7FC25596; assign wn_im[1014] = 32'h07D95B9E; // 1014 0.998 0.061 +assign wn_re[1015] = 32'h7FCE0C3E; assign wn_im[1015] = 32'h0710A345; // 1015 0.998 0.055 +assign wn_re[1016] = 32'h7FD8878E; assign wn_im[1016] = 32'h0647D97C; // 1016 0.999 0.049 +assign wn_re[1017] = 32'h7FE1C76B; assign wn_im[1017] = 32'h057F0035; // 1017 0.999 0.043 +assign wn_re[1018] = 32'h7FE9CBC0; assign wn_im[1018] = 32'h04B6195D; // 1018 0.999 0.037 +assign wn_re[1019] = 32'h7FF09478; assign wn_im[1019] = 32'h03ED26E6; // 1019 1.000 0.031 +assign wn_re[1020] = 32'h7FF62182; assign wn_im[1020] = 32'h03242ABF; // 1020 1.000 0.025 +assign wn_re[1021] = 32'h7FFA72D1; assign wn_im[1021] = 32'h025B26D7; // 1021 1.000 0.018 +assign wn_re[1022] = 32'h7FFD885A; assign wn_im[1022] = 32'h01921D20; // 1022 1.000 0.012 +assign wn_re[1023] = 32'h7FFF6216; assign wn_im[1023] = 32'h00C90F88; // 1023 1.000 0.006 + +endmodule diff --git a/hardware/system/avalon_slave.vhd b/hardware/system/avalon_slave.vhd new file mode 100644 index 0000000..64f9394 --- /dev/null +++ b/hardware/system/avalon_slave.vhd @@ -0,0 +1,24 @@ +library ieee; + use ieee.std_logic_1164.all; + +package avalon_slave is + + type State is ( + SLAVE_IDLE, + SLAVE_READ, + SLAVE_READ_DATA, + SLAVE_WRITE + ); + + type Request is record + address : std_logic_vector( 3 downto 0 ); + read : std_logic; + write : std_logic; + writedata : std_logic_vector( 31 downto 0 ); + end record Request; + + type Response is record + readdata : std_logic_vector( 31 downto 0 ); + end record Response; + +end package avalon_slave; diff --git a/hardware/system/avalon_slave_transitions.vhd b/hardware/system/avalon_slave_transitions.vhd new file mode 100644 index 0000000..a1c04c1 --- /dev/null +++ b/hardware/system/avalon_slave_transitions.vhd @@ -0,0 +1,89 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.avalon_slave.all; + +entity avalon_slave_transitions is + generic ( + REG_COUNT : natural; + REG_ACCESS_TYPES : work.reg32.AccessArray + ); + port ( + address : in std_logic_vector( 3 downto 0 ); + read : in std_logic; + write : in std_logic; + + current_state : in work.avalon_slave.State; + next_state : out work.avalon_slave.State; + reg_index : out integer range 0 to REG_COUNT - 1 + ); +end entity avalon_slave_transitions; + +architecture rtl of avalon_slave_transitions is + + signal is_access : boolean; + signal is_read : boolean; + signal is_write : boolean; + signal address_index : integer range 0 to 2 ** address'high - 1; + signal is_valid_reg_index : boolean; + signal access_type : work.reg32.AccessType; + signal is_valid_access : boolean; + signal is_valid_access_type : boolean; + signal index : integer range 0 to REG_COUNT - 1; + +begin + + c_is_access: is_access <= ( read or write ) = '1'; + c_is_read: is_read <= read = '1'; + c_is_write: is_write <= write = '1' and not is_read; + + c_address_index: address_index <= to_integer( unsigned( address ) ); + + c_is_valid_reg_index: is_valid_reg_index <= address_index <= ( REG_COUNT - 1 ); + + c_index: index <= address_index when is_valid_reg_index else 0; + c_reg_index: reg_index <= index; + + c_access_type: access_type <= REG_ACCESS_TYPES( index ); + + c_is_valid_access_type: is_valid_access_type <= true when + ( is_read and work.reg32.allows_read( access_type ) ) or + ( is_write and work.reg32.allows_write( access_type ) ) + else false; + + c_is_valid_access: is_valid_access <= is_access and is_valid_reg_index and + is_valid_access_type; + + transition : process( all ) is + begin + case current_state is + when SLAVE_IDLE => + if ( is_valid_access and is_read ) then + next_state <= SLAVE_READ; + elsif ( is_valid_access and is_write ) then + next_state <= SLAVE_WRITE; + else + next_state <= SLAVE_IDLE; + end if; + + when SLAVE_READ => + next_state <= SLAVE_READ_DATA; + + when SLAVE_READ_DATA => + if ( is_valid_access and is_read ) then + next_state <= SLAVE_READ; + elsif ( is_valid_access and is_write ) then + next_state <= SLAVE_WRITE; + else + next_state <= SLAVE_IDLE; + end if; + + when SLAVE_WRITE => + next_state <= SLAVE_IDLE; + end case; + end process transition; + +end architecture rtl; diff --git a/hardware/system/cordic.vhd b/hardware/system/cordic.vhd new file mode 100644 index 0000000..ef3c851 --- /dev/null +++ b/hardware/system/cordic.vhd @@ -0,0 +1,120 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +library work; + use work.cordic_pkg.all; + +entity cordic is + generic ( + SIZE : positive; + ITERATIONS : positive; + RESET_ACTIVE_LEVEL : std_ulogic := '1' + ); + port ( + Clock : in std_ulogic; + Reset : in std_ulogic; + + Data_valid : in std_ulogic; --# Load new input data + Busy : out std_ulogic; --# Generating new result + Result_valid : out std_ulogic; --# Flag when result is valid + Mode : in cordic_mode; --# Rotation or vector mode selection + + X : in signed(SIZE-1 downto 0); + Y : in signed(SIZE-1 downto 0); + Z : in signed(SIZE-1 downto 0); + + X_result : out signed(SIZE-1 downto 0); + Y_result : out signed(SIZE-1 downto 0); + Z_result : out signed(SIZE-1 downto 0) + ); +end entity; + +architecture rtl of cordic is + type signed_array is array (natural range <>) of signed(SIZE-1 downto 0); + + function gen_atan_table(s : positive) return signed_array is + variable table : signed_array(0 to ITERATIONS-1); + begin + for i in table'range loop + table(i) := to_signed(integer(arctan(2.0**(-i)) * 2.0**s / MATH_2_PI), s); + end loop; + + return table; + end function; + + constant ATAN_TABLE : signed_array(0 to ITERATIONS-1) := gen_atan_table(SIZE); + + signal xr : signed(X'range); + signal yr : signed(Y'range); + signal zr : signed(Z'range); + + signal x_shift : signed(X'range); + signal y_shift : signed(Y'range); + + subtype iter_count is integer range 0 to ITERATIONS; + + signal cur_iter : iter_count; +begin + + p_cordic: process(Clock, Reset) is + variable negative : boolean; + begin + if Reset = RESET_ACTIVE_LEVEL then + xr <= (others => '0'); + yr <= (others => '0'); + zr <= (others => '0'); + cur_iter <= 0; + Result_valid <= '0'; + Busy <= '0'; + elsif rising_edge(Clock) then + if Data_valid = '1' then + xr <= X; + yr <= Y; + zr <= Z; + cur_iter <= 0; + Result_valid <= '0'; + Busy <= '1'; + else + if cur_iter /= ITERATIONS then + --if cur_iter(ITERATIONS) /= '1' then + if Mode = cordic_rotate then + negative := zr(z'high) = '1'; + else + negative := yr(y'high) = '0'; + end if; + + --if zr(z'high) = '1' then -- z or y is negative + if negative then + xr <= xr + y_shift; --(yr / 2**(cur_iter)); + yr <= yr - x_shift; --(xr / 2**(cur_iter)); + zr <= zr + ATAN_TABLE(cur_iter); + else -- z or y is positive + xr <= xr - y_shift; --(yr / 2**(cur_iter)); + yr <= yr + x_shift; --(xr / 2**(cur_iter)); + zr <= zr - ATAN_TABLE(cur_iter); + end if; + + cur_iter <= cur_iter + 1; + --cur_iter <= '0' & cur_iter(0 to ITERATIONS-1); + end if; + + if cur_iter = ITERATIONS-1 then + Result_valid <= '1'; + Busy <= '0'; + end if; + end if; + + end if; + end process; + + x_shift <= shift_right(xr, cur_iter); + y_shift <= shift_right(yr, cur_iter); + + + X_result <= xr; + Y_result <= yr; + Z_result <= zr; + +end architecture; diff --git a/hardware/system/cordic_pkg.vhd b/hardware/system/cordic_pkg.vhd new file mode 100644 index 0000000..ead283c --- /dev/null +++ b/hardware/system/cordic_pkg.vhd @@ -0,0 +1,45 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +package cordic_pkg is + type cordic_mode is (cordic_rotate, cordic_vector); + + function cordic_gain(Iterations : positive) return real; + + procedure adjust_angle(x, y, z : in signed; signal xa, ya, za : out signed); +end package cordic_pkg; + +package body cordic_pkg is + function cordic_gain(iterations : positive) return real is + variable g : real := 1.0; + begin + for i in 0 to iterations-1 loop + g := g * sqrt(1.0 + 2.0**(-2*i)); + end loop; + return g; + end function; + + procedure adjust_angle(x, y, z : in signed; signal xa, ya, za : out signed) is + variable quad : unsigned(1 downto 0); + variable zp : signed(z'length-1 downto 0) := z; + variable yp : signed(y'length-1 downto 0) := y; + variable xp : signed(x'length-1 downto 0) := x; + begin + + -- 0-based quadrant number of angle + quad := unsigned(zp(zp'high downto zp'high-1)); + + if quad = 1 or quad = 2 then -- Rotate into quadrant 0 and 3 (right half of plane) + xp := -xp; + yp := -yp; + -- Add 180 degrees (flip the sign bit) + zp := (not zp(zp'left)) & zp(zp'left-1 downto 0); + end if; + + xa <= xp; + ya <= yp; + za <= zp; + end procedure; +end package body cordic_pkg; diff --git a/hardware/system/data_channel.cmp.vhd b/hardware/system/data_channel.cmp.vhd new file mode 100644 index 0000000..e988772 --- /dev/null +++ b/hardware/system/data_channel.cmp.vhd @@ -0,0 +1,25 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity data_channel is + generic ( + DEPTH : positive := 1024 + ); + port ( + clk : in std_logic; + reset : in std_logic; + + ctrl_address : in std_logic_vector( 3 downto 0 ); + ctrl_read : in std_logic; + ctrl_readdata : out std_logic_vector( 31 downto 0 ); + ctrl_write : in std_logic; + ctrl_writedata : in std_logic_vector( 31 downto 0 ); + + hw_sink_write : in std_logic; + hw_sink_writedata : in std_logic_vector( 31 downto 0 ); + + hw_source_read : in std_logic; + hw_source_readdata : out std_logic_vector( 31 downto 0 ) + ); +end entity data_channel; + diff --git a/hardware/system/data_channel.vhd b/hardware/system/data_channel.vhd new file mode 100644 index 0000000..1eb962b --- /dev/null +++ b/hardware/system/data_channel.vhd @@ -0,0 +1,122 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity data_channel is + generic ( + DEPTH : positive := 1024 + ); + port ( + clk : in std_logic; + reset : in std_logic; + + ctrl_address : in std_logic_vector( 3 downto 0 ); + ctrl_read : in std_logic; + ctrl_readdata : out std_logic_vector( 31 downto 0 ); + ctrl_write : in std_logic; + ctrl_writedata : in std_logic_vector( 31 downto 0 ); + + hw_sink_write : in std_logic; + hw_sink_writedata : in std_logic_vector( 31 downto 0 ); + + hw_source_read : in std_logic; + hw_source_readdata : out std_logic_vector( 31 downto 0 ) + ); +end entity data_channel; + +architecture struct of data_channel is + + signal sink_config : std_logic; + signal source_config : std_logic; + + signal clear : std_logic; + signal empty : std_logic; + signal full : std_logic; + signal level : std_logic_vector( 9 downto 0 ); + + signal ctrl_sink_write : std_logic; + signal ctrl_sink_writedata : std_logic_vector( 31 downto 0 ); + + signal ctrl_source_read : std_logic; + signal ctrl_source_readdata : std_logic_vector( 31 downto 0 ); + + signal sink_write : std_logic; + signal sink_writedata : std_logic_vector( 31 downto 0 ); + + signal source_read : std_logic; + signal source_readdata : std_logic_vector( 31 downto 0 ); + +begin + + u_control : entity work.data_channel_control + port map ( + clk => clk, + reset => reset, + + address => ctrl_address, + read => ctrl_read, + readdata => ctrl_readdata, + write => ctrl_write, + writedata => ctrl_writedata, + + sink_config => sink_config, + source_config => source_config, + + clear => clear, + empty => empty, + full => full, + level => level, + + sink_write => ctrl_sink_write, + sink_writedata => ctrl_sink_writedata, + + source_read => ctrl_source_read, + source_readdata => ctrl_source_readdata + ); + + u_data_sink_mux : entity work.data_sink_mux + port map ( + sel => sink_config, + + sw_write => ctrl_sink_write, + sw_writedata => ctrl_sink_writedata, + + hw_write => hw_sink_write, + hw_writedata => hw_sink_writedata, + + write => sink_write, + writedata => sink_writedata + ); + + u_fifo : entity work.fifo + generic map ( + DEPTH => DEPTH + ) + port map ( + aclr => reset, + clock => clk, + sclr => clear, + data => sink_writedata, + rdreq => source_read, + wrreq => sink_write, + empty => empty, + full => full, + q => source_readdata, + usedw => level + ); + + u_data_source_mux : entity work.data_source_mux + port map ( + sel => source_config, + + sw_read => ctrl_source_read, + sw_readdata => ctrl_source_readdata, + + hw_read => hw_source_read, + hw_readdata => hw_source_readdata, + + read => source_read, + readdata => source_readdata + ); + +end architecture; diff --git a/hardware/system/data_channel_control.vhd b/hardware/system/data_channel_control.vhd new file mode 100644 index 0000000..7dbd9ac --- /dev/null +++ b/hardware/system/data_channel_control.vhd @@ -0,0 +1,151 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.avalon_slave.all; + +entity data_channel_control is + port ( + clk : in std_logic; + reset : in std_logic; + + address : in std_logic_vector( 3 downto 0 ); + read : in std_logic; + readdata : out std_logic_vector( 31 downto 0 ); + write : in std_logic; + writedata : in std_logic_vector( 31 downto 0 ); + + sink_config : out std_logic; + source_config : out std_logic; + + clear : out std_logic; + empty : in std_logic; + full : in std_logic; + level : in std_logic_vector( 9 downto 0 ); + + sink_write : out std_logic; + sink_writedata : out std_logic_vector( 31 downto 0 ); + + source_read : out std_logic; + source_readdata : in std_logic_vector( 31 downto 0 ) + ); +end entity data_channel_control; + +architecture rtl of data_channel_control is + + type Registers is ( + REG_CONFIG, + REG_EMPTY, + REG_FULL, + REG_LEVEL, + REG_SINK, + REG_SOURCE, + REG_CLEAR + ); + + constant REG_CONFIG_POS : natural := Registers'pos( REG_CONFIG ); + constant REG_EMPTY_POS : natural := Registers'pos( REG_EMPTY ); + constant REG_FULL_POS : natural := Registers'pos( REG_FULL ); + constant REG_LEVEL_POS : natural := Registers'pos( REG_LEVEL ); + constant REG_SINK_POS : natural := Registers'pos( REG_SINK ); + constant REG_SOURCE_POS : natural := Registers'pos( REG_SOURCE ); + constant REG_CLEAR_POS : natural := Registers'pos( REG_CLEAR ); + + constant REG_COUNT : natural := registers'pos( registers'right ) + 1; + + constant REG_ACCESS_TYPES : work.reg32.AccessArray( 0 to REG_COUNT - 1 ) := ( + READ_WRITE, + READ_ONLY, + READ_ONLY, + READ_ONLY, + WRITE_ONLY, + READ_ONLY, + WRITE_ONLY + ); + + signal reg_index : integer range 0 to REG_COUNT - 1; + + -- Internal registers + signal current_state : work.avalon_slave.State; + signal next_state : work.avalon_slave.State; + signal reg_data : RegArray( 0 to REG_COUNT - 1 ); + signal fifo_read_req : std_logic; + +begin + + u_avalon_slave_transitions: entity work.avalon_slave_transitions + generic map ( + REG_COUNT => REG_COUNT, + REG_ACCESS_TYPES => REG_ACCESS_TYPES + ) + port map ( + address => address, + read => read, + write => write, + + current_state => current_state, + next_state => next_state, + reg_index => reg_index + ); + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_state <= SLAVE_IDLE; + reg_data( REG_CONFIG_POS ) <= ( others => '0' ); + fifo_read_req <= '0'; + clear <= '0'; + + elsif ( rising_edge( clk ) ) then + current_state <= next_state; + sink_write <= '0'; + source_read <= '0'; + clear <= '0'; + + case next_state is + when SLAVE_IDLE => + null; + + when SLAVE_READ => + readdata <= ( others => '0' ); + if ( reg_index = REG_CONFIG_POS ) then + readdata( 1 downto 0 ) <= reg_data( reg_index )( 1 downto 0 ); + elsif ( reg_index = REG_EMPTY_POS ) then + readdata( 0 ) <= reg_data( reg_index )( 0 ); + elsif ( reg_index = REG_FULL_POS ) then + readdata( 0 ) <= reg_data( reg_index )( 0 ); + elsif ( reg_index = REG_LEVEL_POS ) then + readdata( 9 downto 0 ) <= reg_data( reg_index )( 9 downto 0 ); + elsif ( reg_index = REG_SINK_POS ) then + readdata <= reg_data( reg_index ); + elsif ( reg_index = REG_SOURCE_POS ) then + readdata <= source_readdata; + source_read <= '1'; + end if; + when SLAVE_READ_DATA => + null; + + when SLAVE_WRITE => + if ( reg_index = REG_SINK_POS ) then + sink_write <= '1'; + sink_writedata <= writedata; + elsif ( reg_index = REG_CLEAR_POS ) then + clear <= '1'; + else + reg_data( reg_index ) <= writedata; + end if; + end case; + + reg_data( REG_EMPTY_POS )( 0 ) <= empty; + reg_data( REG_FULL_POS )( 0 ) <= full; + reg_data( REG_LEVEL_POS )( level'left downto level'right ) <= level; + end if; + end process sync; + + sink_config <= reg_data( REG_CONFIG_POS )( 0 ); + source_config <= reg_data( REG_CONFIG_POS )( 1 ); + +end architecture rtl; + diff --git a/hardware/system/data_channel_hw.tcl b/hardware/system/data_channel_hw.tcl new file mode 100644 index 0000000..04855d4 --- /dev/null +++ b/hardware/system/data_channel_hw.tcl @@ -0,0 +1,194 @@ +# TCL File Generated by Component Editor 20.1 +# Tue Jun 14 23:19:06 CEST 2022 +# DO NOT MODIFY + + +# +# data_channel "data_channel" v1.0 +# Johannes Kutning 2022.06.14.23:19:06 +# A data channel between two tasks +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module data_channel +# +set_module_property DESCRIPTION "A data channel between two tasks" +set_module_property NAME data_channel +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP signal_processing +set_module_property AUTHOR "Johannes Kutning" +set_module_property DISPLAY_NAME data_channel +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL data_channel +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file data_channel.vhd VHDL PATH data_channel.vhd TOP_LEVEL_FILE + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL data_channel +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file data_channel.vhd VHDL PATH data_channel.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point ctrl +# +add_interface ctrl avalon end +set_interface_property ctrl addressUnits WORDS +set_interface_property ctrl associatedClock clock +set_interface_property ctrl associatedReset reset +set_interface_property ctrl bitsPerSymbol 8 +set_interface_property ctrl burstOnBurstBoundariesOnly false +set_interface_property ctrl burstcountUnits WORDS +set_interface_property ctrl explicitAddressSpan 0 +set_interface_property ctrl holdTime 0 +set_interface_property ctrl linewrapBursts false +set_interface_property ctrl maximumPendingReadTransactions 0 +set_interface_property ctrl maximumPendingWriteTransactions 0 +set_interface_property ctrl readLatency 0 +set_interface_property ctrl readWaitTime 1 +set_interface_property ctrl setupTime 0 +set_interface_property ctrl timingUnits Cycles +set_interface_property ctrl writeWaitTime 0 +set_interface_property ctrl ENABLED true +set_interface_property ctrl EXPORT_OF "" +set_interface_property ctrl PORT_NAME_MAP "" +set_interface_property ctrl CMSIS_SVD_VARIABLES "" +set_interface_property ctrl SVD_ADDRESS_GROUP "" + +add_interface_port ctrl ctrl_address address Input 4 +add_interface_port ctrl ctrl_read read Input 1 +add_interface_port ctrl ctrl_readdata readdata Output 32 +add_interface_port ctrl ctrl_write write Input 1 +add_interface_port ctrl ctrl_writedata writedata Input 32 +set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 +set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point hw_sink +# +add_interface hw_sink avalon end +set_interface_property hw_sink addressUnits WORDS +set_interface_property hw_sink associatedClock clock +set_interface_property hw_sink associatedReset reset +set_interface_property hw_sink bitsPerSymbol 8 +set_interface_property hw_sink burstOnBurstBoundariesOnly false +set_interface_property hw_sink burstcountUnits WORDS +set_interface_property hw_sink explicitAddressSpan 0 +set_interface_property hw_sink holdTime 0 +set_interface_property hw_sink linewrapBursts false +set_interface_property hw_sink maximumPendingReadTransactions 0 +set_interface_property hw_sink maximumPendingWriteTransactions 0 +set_interface_property hw_sink readLatency 0 +set_interface_property hw_sink readWaitTime 1 +set_interface_property hw_sink setupTime 0 +set_interface_property hw_sink timingUnits Cycles +set_interface_property hw_sink writeWaitTime 0 +set_interface_property hw_sink ENABLED true +set_interface_property hw_sink EXPORT_OF "" +set_interface_property hw_sink PORT_NAME_MAP "" +set_interface_property hw_sink CMSIS_SVD_VARIABLES "" +set_interface_property hw_sink SVD_ADDRESS_GROUP "" + +add_interface_port hw_sink hw_sink_write write Input 1 +add_interface_port hw_sink hw_sink_writedata writedata Input 32 +set_interface_assignment hw_sink embeddedsw.configuration.isFlash 0 +set_interface_assignment hw_sink embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment hw_sink embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment hw_sink embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point hw_source +# +add_interface hw_source avalon end +set_interface_property hw_source addressUnits WORDS +set_interface_property hw_source associatedClock clock +set_interface_property hw_source associatedReset reset +set_interface_property hw_source bitsPerSymbol 8 +set_interface_property hw_source burstOnBurstBoundariesOnly false +set_interface_property hw_source burstcountUnits WORDS +set_interface_property hw_source explicitAddressSpan 0 +set_interface_property hw_source holdTime 0 +set_interface_property hw_source linewrapBursts false +set_interface_property hw_source maximumPendingReadTransactions 0 +set_interface_property hw_source maximumPendingWriteTransactions 0 +set_interface_property hw_source readLatency 0 +set_interface_property hw_source readWaitTime 1 +set_interface_property hw_source setupTime 0 +set_interface_property hw_source timingUnits Cycles +set_interface_property hw_source writeWaitTime 0 +set_interface_property hw_source ENABLED true +set_interface_property hw_source EXPORT_OF "" +set_interface_property hw_source PORT_NAME_MAP "" +set_interface_property hw_source CMSIS_SVD_VARIABLES "" +set_interface_property hw_source SVD_ADDRESS_GROUP "" + +add_interface_port hw_source hw_source_read read Input 1 +add_interface_port hw_source hw_source_readdata readdata Output 32 +set_interface_assignment hw_source embeddedsw.configuration.isFlash 0 +set_interface_assignment hw_source embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment hw_source embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment hw_source embeddedsw.configuration.isPrintableDevice 0 + diff --git a/hardware/system/data_sink_mux.vhd b/hardware/system/data_sink_mux.vhd new file mode 100644 index 0000000..e2a1688 --- /dev/null +++ b/hardware/system/data_sink_mux.vhd @@ -0,0 +1,26 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity data_sink_mux is + port ( + sel : in std_logic; + + sw_write : in std_logic; + sw_writedata : in std_logic_vector( 31 downto 0 ); + + hw_write : in std_logic; + hw_writedata : in std_logic_vector( 31 downto 0 ); + + write : out std_logic; + writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity data_sink_mux; + +architecture rtl of data_sink_mux is +begin + write <= sw_write when sel = '0' else hw_write; + + writedata <= sw_writedata when sel = '0' else + hw_writedata; + +end architecture rtl; diff --git a/hardware/system/data_source_mux.vhd b/hardware/system/data_source_mux.vhd new file mode 100644 index 0000000..9f55185 --- /dev/null +++ b/hardware/system/data_source_mux.vhd @@ -0,0 +1,26 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity data_source_mux is + port ( + sel : in std_logic; + + sw_read : in std_logic; + sw_readdata : out std_logic_vector( 31 downto 0 ); + + hw_read : in std_logic; + hw_readdata : out std_logic_vector( 31 downto 0 ); + + read : out std_logic; + readdata : in std_logic_vector( 31 downto 0 ) + ); +end entity data_source_mux; + +architecture rtl of data_source_mux is +begin + read <= sw_read when sel = '0' else hw_read; + + sw_readdata <= readdata; + hw_readdata <= readdata; + +end architecture rtl; diff --git a/hardware/system/fft_magnitude_calc.vhd b/hardware/system/fft_magnitude_calc.vhd new file mode 100644 index 0000000..50fbffb --- /dev/null +++ b/hardware/system/fft_magnitude_calc.vhd @@ -0,0 +1,180 @@ +------------------------------------------------------------------------ +-- fft_magnitude_calc +-- +-- calculation of FFT magnitude sqrt(real_part²+im_part²) +-- Inputs: +-- input_re in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K) +-- input_im in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K) +-- input_valid: high = inputs are valid for data processing +-- Outputs +-- output_magnitude: Fixpoint 0.5=0x40000000 (always positive) +-- output_valid: high = magnitude data is valid +----------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.task.all; + use work.float.all; + +entity fft_magnitude_calc is + port ( + clk : in std_logic; + reset : in std_logic; + + input_valid: in std_logic; + input_re : in std_logic_vector( 31 downto 0 ); -- in Fixpoint + input_im : in std_logic_vector( 31 downto 0 ); -- in Fixpoint + + output_valid : out std_logic; + output_magnitude : out std_logic_vector( 31 downto 0 ) + ); +end entity fft_magnitude_calc; + +architecture rtl of fft_magnitude_calc is + + subtype Word_64 is std_logic_vector( 63 downto 0 ); + type Array_64 is array ( natural range <> ) of Word_64; + + subtype Word_32 is std_logic_vector( 31 downto 0 ); + type Array_32 is array ( natural range <> ) of Word_32; + + subtype Word_16 is std_logic_vector( 15 downto 0 ); + type Array_16 is array ( natural range <> ) of Word_16; + + signal input_valid_stage1 : std_logic; + signal re_multiply_re_stage1 : signed(63 downto 0); + signal im_multiply_re_stage1 : signed(63 downto 0); + + signal input_valid_stage2 : std_logic; + signal re2_add_im2 : signed(63 downto 0); + + signal input_valid_stage3 : std_logic; + signal input_sqrt : Array_32( 0 to 16 ); + signal output_sqrt: Array_16( 0 to 16 ); + + signal output_delay_sqrt: std_logic_vector(15 downto 0); + + signal data_memory : work.reg32.RegArray( 0 to 1023 ); + signal index_sqrt : integer range 0 to 16; + +begin + + + -- calculation of real_part² and im_part² + p_pow2_stage1: process ( clk, reset ) is + begin + if ( reset = '1' ) then + input_valid_stage1 <= '0'; + re_multiply_re_stage1 <= (others => '0'); + im_multiply_re_stage1 <= (others => '0'); + elsif ( rising_edge( clk ) ) then + input_valid_stage1 <= input_valid; + if input_valid = '1' then + re_multiply_re_stage1 <= signed(input_re) * signed(input_re); + im_multiply_re_stage1 <= signed(input_im) * signed(input_im); + end if; + end if; + end process p_pow2_stage1; + + -- calculation of real_part²*+im_part² + p_add_stage2: process ( clk, reset ) is + begin + if ( reset = '1' ) then + input_valid_stage2 <= '0'; + re2_add_im2 <= (others => '0'); + elsif ( rising_edge( clk ) ) then + input_valid_stage2 <= input_valid_stage1; + re2_add_im2 <= re_multiply_re_stage1 + im_multiply_re_stage1; + end if; + end process p_add_stage2; + + -- calculation of sqrt (one sqrt caluation needs 16 clks with G_DATA_W => 32 + -- for continous stream 17 sqrt instances are needed + p_sqrt_stage3: process ( clk, reset ) is + begin + if ( reset = '1' ) then + input_valid_stage3 <= '0'; + index_sqrt <= 0; + input_sqrt(0) <= (others => '0'); + input_sqrt(1) <= (others => '0'); + input_sqrt(2) <= (others => '0'); + input_sqrt(3) <= (others => '0'); + input_sqrt(4) <= (others => '0'); + input_sqrt(5) <= (others => '0'); + input_sqrt(6) <= (others => '0'); + input_sqrt(7) <= (others => '0'); + input_sqrt(8) <= (others => '0'); + input_sqrt(9) <= (others => '0'); + input_sqrt(10) <= (others => '0'); + input_sqrt(11) <= (others => '0'); + input_sqrt(12) <= (others => '0'); + input_sqrt(13) <= (others => '0'); + input_sqrt(14) <= (others => '0'); + input_sqrt(15) <= (others => '0'); + input_sqrt(16) <= (others => '0'); + elsif ( rising_edge( clk ) ) then + input_valid_stage3 <= input_valid_stage2; + if input_valid_stage2 = '1' then + if index_sqrt = 16 then + index_sqrt <= 0; + else + index_sqrt <= index_sqrt +1; + end if; + end if; + case index_sqrt is + when 16 => input_sqrt(16) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 15 => input_sqrt(15) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 14 => input_sqrt(14) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 13 => input_sqrt(13) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 12 => input_sqrt(12) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 11 => input_sqrt(11) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 10 => input_sqrt(10) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 9 => input_sqrt(9) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 8 => input_sqrt(8) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 7 => input_sqrt(7) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 6 => input_sqrt(6) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 5 => input_sqrt(5) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 4 => input_sqrt(4) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 3 => input_sqrt(3) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 2 => input_sqrt(2) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 1 => input_sqrt(1) <= std_logic_vector(re2_add_im2(63 downto 32)); + when 0 => input_sqrt(0) <= std_logic_vector(re2_add_im2(63 downto 32)); + when others => null; + end case; + end if; + end process p_sqrt_stage3; + + -- generate sqrt instances for continous data stream + gen_sqrt_array: for i in 0 to 16 generate + sqrt_module : entity work.squareRoot_pipe + generic map ( + G_DATA_W => 32 + ) + port map ( + clk => clk, + rst => reset, + iv_data => input_sqrt(i), + ov_res => output_sqrt(i) + ); + end generate gen_sqrt_array; + + -- output assignment + p_output_stage4: process ( clk, reset ) is + begin + if ( reset = '1' ) then + output_valid <= '0'; + output_magnitude <= (others => '0'); + output_delay_sqrt <= (others => '0'); + elsif ( rising_edge( clk ) ) then + output_delay_sqrt <= output_delay_sqrt(14 downto 0) & input_valid_stage3; + output_valid <= output_delay_sqrt(15); + output_magnitude <= std_logic_vector(output_sqrt(index_sqrt)) & x"0000"; + end if; + end process p_output_stage4; + + +end architecture rtl; + diff --git a/hardware/system/fifo.vhd b/hardware/system/fifo.vhd new file mode 100644 index 0000000..a8659de --- /dev/null +++ b/hardware/system/fifo.vhd @@ -0,0 +1,118 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity fifo is + generic ( + DEPTH : positive := 1024 + ); + port + ( + aclr : in std_logic; + clock : in std_logic; + sclr : in std_logic; + data : in std_logic_vector( 31 downto 0 ); + rdreq : in std_logic; + wrreq : in std_logic; + empty : out std_logic; + full : out std_logic; + q : out std_logic_vector( 31 downto 0 ); + usedw : out std_logic_vector( 9 downto 0 ) + ); +end entity fifo; + +architecture rtl of fifo is + + type Operation is ( + OPERATION_IDLE, + OPERATION_CLEAR, + OPERATION_READ, + OPERATION_WRITE, + OPERATION_READ_WRITE + ); + + signal is_empty : boolean; + signal is_full : boolean; + + signal is_read : boolean; + signal is_write : boolean; + signal is_read_write : boolean; + + signal next_operation : Operation; + + signal fifo_data : work.reg32.RegArray( 0 to DEPTH - 1 ); + + signal write_index : integer range 0 to DEPTH - 1; + signal read_index : integer range 0 to DEPTH - 1; + signal item_count : integer range 0 to DEPTH; + + function increment_with_overflow( value : integer; max : integer ) return integer + is + begin + if ( value < max - 1 ) then + return value + 1; + end if; + return 0; + end function increment_with_overflow; + +begin + + c_is_empty: is_empty <= item_count = 0; + c_is_full: is_full <= item_count = DEPTH; + + c_is_read: is_read <= rdreq = '1' and not is_empty; + c_is_write: is_write <= wrreq = '1' and not is_full; + c_is_read_write: is_read_write <= is_read and is_write; + + c_next_operation: next_operation <= OPERATION_CLEAR when sclr + else OPERATION_READ_WRITE when is_read_write + else OPERATION_READ when is_read + else OPERATION_WRITE when is_write + else OPERATION_IDLE; + + sync: process( clock, aclr ) is + begin + if ( aclr = '1' ) then + write_index <= 0; + read_index <= 0; + item_count <= 0; + elsif ( rising_edge( clock ) ) then + + case next_operation is + when OPERATION_IDLE => + null; + + when OPERATION_CLEAR => + write_index <= 0; + read_index <= 0; + item_count <= 0; + + when OPERATION_READ => + item_count <= item_count - 1; + read_index <= increment_with_overflow( read_index, DEPTH ); + + when OPERATION_WRITE => + fifo_data( write_index ) <= data; + item_count <= item_count + 1; + write_index <= increment_with_overflow( write_index, DEPTH ); + + when OPERATION_READ_WRITE => + read_index <= increment_with_overflow( read_index, DEPTH ); + + fifo_data( write_index ) <= data; + write_index <= increment_with_overflow( write_index, DEPTH ); + end case; + + end if; + end process; + + c_assign_q: q <= data when ( is_empty and is_write ) else + fifo_data( read_index ); + + c_assign_usedw: + usedw <= std_logic_vector( to_unsigned( item_count, usedw'length ) ); + + full <= '1' when is_full else '0'; + empty <= '1' when is_empty else '0'; +end architecture rtl; + diff --git a/hardware/system/fixed_sine.vhd b/hardware/system/fixed_sine.vhd new file mode 100644 index 0000000..2915a5b --- /dev/null +++ b/hardware/system/fixed_sine.vhd @@ -0,0 +1,83 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +library work; + use work.cordic_pkg.all; + +entity fixed_sine is + generic ( + SIZE : positive; -- Width of parameters + ITERATIONS : positive; -- Number of CORDIC iterations + FRAC_BITS : positive; -- Total fractional bits + MAGNITUDE : real := 1.0; + RESET_ACTIVE_LEVEL : std_ulogic := '1' + ); + port ( + clock : in std_ulogic; + reset : in std_ulogic; + data_valid : in std_ulogic; --# load new input data + busy : out std_ulogic; --# generating new result + result_valid : out std_ulogic; --# flag when result is valid + angle : in signed(size-1 downto 0); -- angle in brads (2**size brads = 2*pi radians) + sine : out signed(size-1 downto 0) + ); +end entity fixed_sine; + +architecture rtl of fixed_sine is + signal xa, ya, za, x_result, y_result : signed(Angle'range); + signal rv_loc : std_ulogic; +begin + + adj: process(clock, reset) is + constant Y : signed(Angle'range) := (others => '0'); + constant X : signed(Angle'range) := --to_signed(1, Angle'length); + to_signed(integer(MAGNITUDE/cordic_gain(ITERATIONS) * 2.0 ** FRAC_BITS), Angle'length); + begin + if reset = RESET_ACTIVE_LEVEL then + xa <= (others => '0'); + ya <= (others => '0'); + za <= (others => '0'); + elsif rising_edge(clock) then + adjust_angle(X, Y, Angle, xa, ya, za); + end if; + end process; + + c: entity work.cordic + generic map ( + SIZE => SIZE, + ITERATIONS => ITERATIONS, + RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL + ) + port map ( + clock => clock, + reset => reset, + data_valid => data_valid, + result_valid => rv_loc, + busy => busy, + Mode => cordic_rotate, + + X => xa, + Y => ya, + Z => za, + + X_result => x_result, + Y_result => y_result, + Z_result => open + ); + + reg: process(clock, reset) is + begin + if reset = RESET_ACTIVE_LEVEL then + sine <= (others => '0'); + result_valid <= '0'; + elsif rising_edge(clock) then + result_valid <= rv_loc; + + if rv_loc = '1' then -- Capture result + sine <= y_result; + end if; + end if; + end process; +end architecture; diff --git a/hardware/system/float.vhd b/hardware/system/float.vhd new file mode 100644 index 0000000..889f217 --- /dev/null +++ b/hardware/system/float.vhd @@ -0,0 +1,144 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package float is + constant SIGN : std_logic_vector( 31 downto 31 ) := ( others => '0' ); + constant EXP : std_logic_vector( 30 downto 23 ) := ( others => '0' ); + constant MANTISSA : std_logic_vector( 22 downto 0 ) := ( others => '0' ); + + function find_leftmost( arg : unsigned; value : std_ulogic ) return integer; + + function count_leading_digits( arg : unsigned; value : std_ulogic ) return integer; + + function to_float( arg : std_logic_vector ) return std_logic_vector; + + function to_fixed( arg : std_logic_vector ) return std_logic_vector; + +end package float; + +package body float is + function find_leftmost( arg : unsigned; value : std_ulogic ) return integer is + begin + for i in arg'left downto arg'right loop + if ( arg( i ) = value ) then + return i; + end if; + end loop; + + return -1; + end function find_leftmost; + + function count_leading_digits( arg : unsigned; value : std_ulogic ) return integer is + variable left_most_value : integer range -1 to arg'high; + variable leading_values : integer range 0 to arg'high; + begin + left_most_value := find_leftmost( arg, not value ); + leading_values := 0; + + if ( left_most_value /= -1 ) then + leading_values := arg'high - left_most_value; + end if; + + return leading_values; + end function count_leading_digits; + + function to_float( arg : std_logic_vector ) return std_logic_vector is + variable y : std_logic_vector( 31 downto 0 ); + variable s : std_logic; + variable e : unsigned( 7 downto 0 ); + variable m : unsigned( 22 downto 0 ); + variable value : unsigned( 30 downto 0 ); + + variable leading_sign_digits : integer range 0 to value'high; + variable reminding : integer range 0 to value'high; + begin + s := arg( 31 ); + + if ( s = '0' ) then + value := unsigned( arg( 30 downto 0 ) ); + else + value := not unsigned( arg( 30 downto 0 ) ); + value := value +1; + end if; + leading_sign_digits := count_leading_digits( value, '0' ); + reminding := value'high - leading_sign_digits; + e := to_unsigned( 126 - leading_sign_digits, e'length ); + + if ( reminding > m'length ) then + m := value( reminding - 1 downto reminding - m'length ); + elsif ( reminding > 1 ) then + m := ( others => '0' ); + m( m'high downto m'high - reminding + 1 ) := value( reminding - 1 downto 0 ); + else + m := ( others => '0' ); + end if; + + if (arg = x"00000000") then + y := (others => '0'); + else + y := s & std_logic_vector( e ) & std_logic_vector( m ); + end if; + + return y; + end function to_float; + + function to_fixed( arg : std_logic_vector ) return std_logic_vector is + variable y : unsigned( 31 downto 0 ); + variable s : std_logic; + variable e : unsigned( 7 downto 0 ); + variable m_index_max : integer range -127 to 128; + + begin + s := arg( 31 ); + e := unsigned(arg(30 downto 23)); + m_index_max := to_integer(signed(30-(126-e))); + + if (arg = x"00000000") then + y := (others => '0'); + else + y := (others => '0'); + case m_index_max is + when 30 => y(30 downto 7):= '1' & unsigned( arg(22 downto 0) ); + when 29 => y(29 downto 6):= '1' & unsigned( arg(22 downto 0) ); + when 28 => y(28 downto 5):= '1' & unsigned( arg(22 downto 0) ); + when 27 => y(27 downto 4):= '1' & unsigned( arg(22 downto 0) ); + when 26 => y(26 downto 3):= '1' & unsigned( arg(22 downto 0) ); + when 25 => y(25 downto 2):= '1' & unsigned( arg(22 downto 0) ); + when 24 => y(24 downto 1):= '1' & unsigned( arg(22 downto 0) ); + when 23 => y(23 downto 0):= '1' & unsigned( arg(22 downto 0) ); + when 22 => y(22 downto 0):= '1' & unsigned( arg(22 downto 1) ); + when 21 => y(21 downto 0):= '1' & unsigned( arg(22 downto 2) ); + when 20 => y(20 downto 0):= '1' & unsigned( arg(22 downto 3) ); + when 19 => y(19 downto 0):= '1' & unsigned( arg(22 downto 4) ); + when 18 => y(18 downto 0):= '1' & unsigned( arg(22 downto 5) ); + when 17 => y(17 downto 0):= '1' & unsigned( arg(22 downto 6) ); + when 16 => y(16 downto 0):= '1' & unsigned( arg(22 downto 7) ); + when 15 => y(15 downto 0):= '1' & unsigned( arg(22 downto 8) ); + when 14 => y(14 downto 0):= '1' & unsigned( arg(22 downto 9) ); + when 13 => y(13 downto 0):= '1' & unsigned( arg(22 downto 10) ); + when 12 => y(12 downto 0):= '1' & unsigned( arg(22 downto 11) ); + when 11 => y(11 downto 0):= '1' & unsigned( arg(22 downto 12) ); + when 10 => y(10 downto 0):= '1' & unsigned( arg(22 downto 13) ); + when 9 => y(9 downto 0):= '1' & unsigned( arg(22 downto 14) ); + when 8 => y(8 downto 0):= '1' & unsigned( arg(22 downto 15) ); + when 7 => y(7 downto 0):= '1' & unsigned( arg(22 downto 16) ); + when 6 => y(6 downto 0):= '1' & unsigned( arg(22 downto 17) ); + when 5 => y(5 downto 0):= '1' & unsigned( arg(22 downto 18) ); + when 4 => y(4 downto 0):= '1' & unsigned( arg(22 downto 19) ); + when 3 => y(3 downto 0):= '1' & unsigned( arg(22 downto 20) ); + when 2 => y(2 downto 0):= '1' & unsigned( arg(22 downto 21) ); + when 1 => y(1 downto 0):= '1' & unsigned( arg(22 downto 22) ); + when 0 => y(0):= '1'; + when others => null; + end case; + if ( s = '1' ) then + y := not(y); + y:= y + x"00000001"; + end if; + end if; + + return std_logic_vector( y ); + end function to_fixed; + +end package body float; diff --git a/hardware/system/float_add.vhd b/hardware/system/float_add.vhd new file mode 100644 index 0000000..901c59c --- /dev/null +++ b/hardware/system/float_add.vhd @@ -0,0 +1,133 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity float_add is + port(A : in std_logic_vector(31 downto 0); + B : in std_logic_vector(31 downto 0); + clk : in std_logic; + reset : in std_logic; + start : in std_logic; + done : out std_logic; + sum : out std_logic_vector(31 downto 0) + ); +end float_add; + +architecture mixed of float_add is + type ST is (WAIT_STATE, ALIGN_STATE, ADDITION_STATE, NORMALIZE_STATE, OUTPUT_STATE); + signal state : ST := WAIT_STATE; + + ---Internal Signals latched from the inputs + signal A_mantissa, B_mantissa : std_logic_vector (24 downto 0); + signal A_exp, B_exp : std_logic_vector (8 downto 0); + signal A_sgn, B_sgn : std_logic; + + --Internal signals for Output + signal sum_exp: std_logic_vector (8 downto 0); + signal sum_mantissa : std_logic_vector (24 downto 0); + signal sum_sgn : std_logic; + +begin + + Control_Unit : process (clk, reset) is + variable diff : signed(8 downto 0); + begin + if(reset = '1') then + state <= WAIT_STATE; --start in wait state + done <= '0'; + elsif rising_edge(clk) then + case state is + when WAIT_STATE => + if (start = '1') then --wait till start request startes high + A_sgn <= A(31); + A_exp <= '0' & A(30 downto 23); --One bit is added for signed subtraction + A_mantissa <= "01" & A(22 downto 0); --Two bits are added extra, one for leading 1 and other one for storing carry + B_sgn <= B(31); + B_exp <= '0' & B(30 downto 23); + B_mantissa <= "01" & B(22 downto 0); + state <= ALIGN_STATE; + else + state <= WAIT_STATE; + end if; + when ALIGN_STATE => --Compare exponent and align it + --If any num is greater by 2**24, we skip the addition. + if unsigned(A_exp) > unsigned(B_exp) then + --B needs downshifting + diff := signed(A_exp) - signed(B_exp); --Small Alu + if diff > 23 then + sum_mantissa <= A_mantissa; --B insignificant relative to A + sum_exp <= A_exp; + sum_sgn <= A_sgn; + state <= OUTPUT_STATE; --start latch A as output + else + --downshift B to equilabrate B_exp to A_exp + sum_exp <= A_exp; + B_mantissa(24-to_integer(diff) downto 0) <= B_mantissa(24 downto to_integer(diff)); + B_mantissa(24 downto 25-to_integer(diff)) <= (others => '0'); + state <= ADDITION_STATE; + end if; + elsif unsigned(A_exp) < unsigned(B_exp) then --A_exp < B_exp. A needs downshifting + diff := signed(B_exp) - signed(A_exp); -- Small Alu + if diff > 23 then + sum_mantissa <= B_mantissa; --A insignificant relative to B + sum_sgn <= B_sgn; + sum_exp <= B_exp; + state <= OUTPUT_STATE; --start latch B as output + else + --downshift A to equilabrate A_exp to B_exp + sum_exp <= B_exp; + A_mantissa(24-to_integer(diff) downto 0) <= A_mantissa(24 downto to_integer(diff)); + A_mantissa(24 downto 25-to_integer(diff)) <= (others => '0'); + state <= ADDITION_STATE; + end if; + else -- Both exponent is equal. No need to mantissa shift + sum_exp <= A_exp; + state <= ADDITION_STATE; + end if; + when ADDITION_STATE => --Mantissa addition + state <= NORMALIZE_STATE; + if (A_sgn xor B_sgn) = '0' then --signs are the same. Just add them + sum_mantissa <= std_logic_vector((unsigned(A_mantissa) + unsigned(B_mantissa))); --Big Alu + sum_sgn <= A_sgn; --both nums have same sign + --Else subtract smaller from larger and use sign of larger + elsif unsigned(A_mantissa) >= unsigned(B_mantissa) then + sum_mantissa <= std_logic_vector((unsigned(A_mantissa) - unsigned(B_mantissa))); --Big Alu + sum_sgn <= A_sgn; + else + sum_mantissa <= std_logic_vector((unsigned(B_mantissa) - unsigned(A_mantissa))); --Big Alu + sum_sgn <= B_sgn; + end if; + + when NORMALIZE_STATE => --Normalization. + if unsigned(sum_mantissa) = TO_UNSIGNED(0, 25) then + --The sum is 0 + sum_mantissa <= (others => '0'); + sum_exp <= (others => '0'); + state <= OUTPUT_STATE; + elsif(sum_mantissa(24) = '1') then --If sum overflowed we downshift and are done. + sum_mantissa <= '0' & sum_mantissa(24 downto 1); --shift the 1 down + sum_exp <= std_logic_vector((unsigned(sum_exp)+ 1)); + state <= OUTPUT_STATE; + elsif(sum_mantissa(23) = '0') then --in this case we need to upshift + --This iterates the normalization shifts, thus can take many clocks. + sum_mantissa <= sum_mantissa(23 downto 0) & '0'; + sum_exp <= std_logic_vector((unsigned(sum_exp)-1)); + state<= NORMALIZE_STATE; --keep shifting till leading 1 appears + else + state <= OUTPUT_STATE; --leading 1 already there. Latch output + end if; + when OUTPUT_STATE => + sum(22 downto 0) <= sum_mantissa(22 downto 0); + sum(30 downto 23) <= sum_exp(7 downto 0); + sum(31) <= sum_sgn; + done <= '1'; -- signal done + if (start = '0') then -- stay in the state till request ends i.e start is low + done <= '0'; + state <= WAIT_STATE; + end if; + when others => + state <= WAIT_STATE; --Just in case. + end case; + end if; + end process; + +end mixed; diff --git a/hardware/system/float_sine.vhd b/hardware/system/float_sine.vhd new file mode 100644 index 0000000..a2e02c8 --- /dev/null +++ b/hardware/system/float_sine.vhd @@ -0,0 +1,49 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +library work; + use work.cordic_pkg.all; + use work.float.all; + +entity float_sine is + generic ( + ITERATIONS : positive -- Number of CORDIC iterations + ); + port ( + clk : in std_logic; + reset : in std_logic; + + data_valid : in std_logic; --# load new input data + busy : out std_logic; --# generating new result + result_valid : out std_logic; --# flag when result is valid + angle : in signed(31 downto 0); -- angle in brads (2**size brads = 2*pi radians) + sine : out signed(31 downto 0) + ); +end entity float_sine; + +architecture rtl of float_sine is + signal fixed : signed( 31 downto 0 ); +begin + + u_fixed_sine : entity work.fixed_sine + generic map ( + SIZE => 32, + ITERATIONS => 8, + FRAC_BITS => 31 + ) + port map ( + clock => clk, + reset => reset, + + data_valid => data_valid, + busy => busy, + result_valid => result_valid, + angle => angle, + sine => fixed + ); + + sine <= signed( to_float( std_logic_vector( fixed ) ) ); + +end architecture; diff --git a/hardware/system/hardware_task.cmp.vhd b/hardware/system/hardware_task.cmp.vhd new file mode 100644 index 0000000..7c64210 --- /dev/null +++ b/hardware/system/hardware_task.cmp.vhd @@ -0,0 +1,22 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity hardware_task is + port ( + clk : in std_logic; + reset : in std_logic; + + ctrl_address : in std_logic_vector( 3 downto 0 ); + ctrl_read : in std_logic; + ctrl_readdata : out std_logic_vector( 31 downto 0 ); + ctrl_write : in std_logic; + ctrl_writedata : in std_logic_vector( 31 downto 0 ); + + task_address : out std_logic_vector( 3 downto 0 ); + task_read : out std_logic; + task_readdata : in std_logic_vector( 31 downto 0 ); + task_write : out std_logic; + task_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity hardware_task; + diff --git a/hardware/system/hardware_task.vhd b/hardware/system/hardware_task.vhd new file mode 100644 index 0000000..251e448 --- /dev/null +++ b/hardware/system/hardware_task.vhd @@ -0,0 +1,31 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity hardware_task is + port ( + clk : in std_logic; + reset : in std_logic; + + ctrl_address : in std_logic_vector( 3 downto 0 ); + ctrl_read : in std_logic; + ctrl_readdata : out std_logic_vector( 31 downto 0 ); + ctrl_write : in std_logic; + ctrl_writedata : in std_logic_vector( 31 downto 0 ); + + task_address : out std_logic_vector( 3 downto 0 ); + task_read : out std_logic; + task_readdata : in std_logic_vector( 31 downto 0 ); + task_write : out std_logic; + task_writedata : out std_logic_vector( 31 downto 0 ) + ); +end entity hardware_task; + +architecture rtl of hardware_task is +begin + task_address <= ctrl_address; + task_read <= ctrl_read; + ctrl_readdata <= task_readdata; + task_write <= ctrl_write; + task_writedata <= ctrl_writedata; +end architecture rtl; + diff --git a/hardware/system/hardware_task_control.vhd b/hardware/system/hardware_task_control.vhd new file mode 100644 index 0000000..d549b95 --- /dev/null +++ b/hardware/system/hardware_task_control.vhd @@ -0,0 +1,137 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.task.all; + use work.avalon_slave.all; + +entity hardware_task_control is + port ( + clk : in std_logic; + reset : in std_logic; + + address : in std_logic_vector( 3 downto 0 ); + read : in std_logic; + readdata : out std_logic_vector( 31 downto 0 ); + write : in std_logic; + writedata : in std_logic_vector( 31 downto 0 ); + + task_start : out std_logic; + task_state : in work.task.State; + task_config : out work.reg32.RegArray( 0 to 2 ) + ); +end entity hardware_task_control; + +architecture rtl of hardware_task_control is + + type Registers is ( + REG_START, + REG_STATE, + REG_CYCLE_COUNT, + REG_CONFIG_0, + REG_CONFIG_1, + REG_CONFIG_2 + ); + + constant REG_START_POS : natural := Registers'pos( REG_START ); + constant REG_STATE_POS : natural := Registers'pos( REG_STATE ); + constant REG_CYCLE_COUNT_POS : natural := Registers'pos( REG_CYCLE_COUNT ); + constant REG_CONFIG_0_POS : natural := Registers'pos( REG_CONFIG_0 ); + constant REG_CONFIG_1_POS : natural := Registers'pos( REG_CONFIG_1 ); + constant REG_CONFIG_2_POS : natural := Registers'pos( REG_CONFIG_2 ); + + constant REG_COUNT : natural := registers'pos( registers'right ) + 1; + + constant REG_ACCESS_TYPES : work.reg32.AccessArray( 0 to REG_COUNT - 1 ) := ( + WRITE_ONLY, + READ_ONLY, + READ_ONLY, + READ_WRITE, + READ_WRITE, + READ_WRITE + ); + + -- Internal control and data signals + signal reg_index : integer range 0 to REG_COUNT - 1; + + -- Internal registers + signal current_state : work.avalon_slave.State; + signal next_state : work.avalon_slave.State; + signal reg_data : RegArray( 0 to REG_COUNT - 1 ); + signal task_running : std_logic; + +begin + + u_avalon_slave_transitions: entity work.avalon_slave_transitions + generic map ( + REG_COUNT => REG_COUNT, + REG_ACCESS_TYPES => REG_ACCESS_TYPES + ) + port map ( + address => address, + read => read, + write => write, + + current_state => current_state, + next_state => next_state, + reg_index => reg_index + ); + + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_state <= SLAVE_IDLE; + reg_data( Registers'pos( REG_CYCLE_COUNT ) ) <= ( others => '0' ); + reg_data( Registers'pos( REG_CONFIG_0 ) ) <= ( others => '0' ); + + elsif ( rising_edge( clk ) ) then + current_state <= next_state; + task_start <= '0'; + + if ( task_state = work.task.TASK_DONE ) then + task_running <= '0'; + end if; + + case next_state is + when SLAVE_IDLE => + null; + + when SLAVE_READ => + readdata <= ( others => '0' ); + if ( reg_index = REG_STATE_POS ) then + readdata <= to_std_logic_vector( task_state, work.reg32.word'length ); + elsif ( reg_index = REG_CYCLE_COUNT_POS ) then + readdata <= reg_data( REG_CYCLE_COUNT_POS ); + else + readdata <= reg_data( reg_index ); + end if; + + when SLAVE_READ_DATA => + null; + + when SLAVE_WRITE => + + if ( reg_index = REG_START_POS ) then + task_start <= '1'; + reg_data( REG_CYCLE_COUNT_POS ) <= ( others => '0' ); + task_running <= '1'; + else + reg_data( reg_index ) <= writedata; + end if; + + end case; + + if ( task_running = '1' ) then + reg_data( REG_CYCLE_COUNT_POS ) <= + std_logic_vector( + unsigned( + reg_data( REG_CYCLE_COUNT_POS ) ) + 1 ); + end if; + end if; + end process sync; + task_config <= reg_data( REG_CONFIG_0_POS to REG_CONFIG_2_POS ); +end architecture rtl; + diff --git a/hardware/system/hardware_timestamp.cmp.vhd b/hardware/system/hardware_timestamp.cmp.vhd new file mode 100644 index 0000000..8e7569b --- /dev/null +++ b/hardware/system/hardware_timestamp.cmp.vhd @@ -0,0 +1,13 @@ +entity timer is + port ( + clk : in std_logic; + reset : in std_logic; + + address : in std_logic_vector( 3 downto 0 ); + read : in std_logic; + readdata : out std_logic_vector( 31 downto 0 ); + write : in std_logic; + writedata : in std_logic_vector( 31 downto 0 ) + ); +end entity timer; + diff --git a/hardware/system/hardware_timestamp.vhd b/hardware/system/hardware_timestamp.vhd new file mode 100644 index 0000000..f969f06 --- /dev/null +++ b/hardware/system/hardware_timestamp.vhd @@ -0,0 +1,102 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.reg32.all; + use work.avalon_slave.all; + +entity timer is + port ( + clk : in std_logic; + reset : in std_logic; + + address : in std_logic_vector( 3 downto 0 ); + read : in std_logic; + readdata : out std_logic_vector( 31 downto 0 ); + write : in std_logic; + writedata : in std_logic_vector( 31 downto 0 ) + ); +end entity timer; + +architecture rtl of timer is + + type Registers is ( + REG_STATE, + REG_CYCLE_COUNT + ); + + constant REG_STATE_POS : natural := Registers'pos( REG_STATE ); + constant REG_CYCLE_COUNT_POS : natural := Registers'pos( REG_CYCLE_COUNT ); + constant REG_COUNT : natural := Registers'pos( Registers'right ) + 1; + + constant REG_ACCESS_TYPES : work.reg32.AccessArray( 0 to REG_COUNT - 1 ) := ( + READ_WRITE, + READ_ONLY + ); + + signal reg_index : integer range 0 to REG_COUNT - 1; + + signal current_avalon_state : work.avalon_slave.State; + signal next_avalon_state : work.avalon_slave.State; + + signal running : std_logic; + signal cycle_count : unsigned( 31 downto 0 ); + +begin + + u_avalon_slave_transitions: entity work.avalon_slave_transitions + generic map ( + REG_COUNT => REG_COUNT, + REG_ACCESS_TYPES => REG_ACCESS_TYPES + ) + port map ( + address => address, + read => read, + write => write, + + current_state => current_avalon_state, + next_state => next_avalon_state, + reg_index => reg_index + ); + + sync : process ( clk, reset ) is + begin + if ( reset = '1' ) then + current_avalon_state <= SLAVE_IDLE; + running <= '0'; + + elsif ( rising_edge( clk ) ) then + current_avalon_state <= next_avalon_state; + + if ( running = '1' ) then + cycle_count <= cycle_count + 1; + end if; + + case next_avalon_state is + when SLAVE_IDLE => + null; + + when SLAVE_READ => + readdata <= ( others => '0' ); + if ( reg_index = REG_STATE_POS ) then + readdata( 0 ) <= running; + elsif ( reg_index = REG_CYCLE_COUNT_POS ) then + readdata <= std_logic_vector( cycle_count ); + end if; + + when SLAVE_READ_DATA => + null; + + when SLAVE_WRITE => + if ( reg_index = REG_STATE_POS ) then + running <= writedata( 0 ); + if ( writedata( 0 ) = '1' ) then + cycle_count <= ( others => '0' ); + end if; + end if; + + end case; + end if; + end process sync; +end architecture rtl; diff --git a/hardware/system/pll/pll_main.bsf b/hardware/system/pll/pll_main.bsf new file mode 100644 index 0000000..57d0ed7 --- /dev/null +++ b/hardware/system/pll/pll_main.bsf @@ -0,0 +1,82 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "pll_main" (rect 56 -1 87 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) + (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) + (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 48 112)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 112 72)(line_width 1)) + ) + (port + (pt 160 112) + (output) + (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) + (text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8))) + (line (pt 160 112)(pt 112 112)(line_width 1)) + ) + (drawing + (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) + (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) + (text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0))) + (text " altera_pll " (rect 118 128 308 266)(font "Arial" )) + (line (pt 48 32)(pt 112 32)(line_width 1)) + (line (pt 112 32)(pt 112 128)(line_width 1)) + (line (pt 48 128)(pt 112 128)(line_width 1)) + (line (pt 48 32)(pt 48 128)(line_width 1)) + (line (pt 49 52)(pt 49 76)(line_width 1)) + (line (pt 50 52)(pt 50 76)(line_width 1)) + (line (pt 49 92)(pt 49 116)(line_width 1)) + (line (pt 50 92)(pt 50 116)(line_width 1)) + (line (pt 111 52)(pt 111 76)(line_width 1)) + (line (pt 110 52)(pt 110 76)(line_width 1)) + (line (pt 111 92)(pt 111 116)(line_width 1)) + (line (pt 110 92)(pt 110 116)(line_width 1)) + (line (pt 0 0)(pt 160 0)(line_width 1)) + (line (pt 160 0)(pt 160 144)(line_width 1)) + (line (pt 0 144)(pt 160 144)(line_width 1)) + (line (pt 0 0)(pt 0 144)(line_width 1)) + ) +) diff --git a/hardware/system/pll/pll_main.cmp b/hardware/system/pll/pll_main.cmp new file mode 100644 index 0000000..4e557e5 --- /dev/null +++ b/hardware/system/pll/pll_main.cmp @@ -0,0 +1,9 @@ + component pll_main is + port ( + refclk : in std_logic := 'X'; -- clk + rst : in std_logic := 'X'; -- reset + outclk_0 : out std_logic; -- clk + locked : out std_logic -- export + ); + end component pll_main; + diff --git a/hardware/system/pll/pll_main.ppf b/hardware/system/pll/pll_main.ppf new file mode 100644 index 0000000..94710a0 --- /dev/null +++ b/hardware/system/pll/pll_main.ppf @@ -0,0 +1,13 @@ + + + + + + + + + diff --git a/hardware/system/pll/pll_main.qip b/hardware/system/pll/pll_main.qip new file mode 100644 index 0000000..717613c --- /dev/null +++ b/hardware/system/pll/pll_main.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_main" -name MISC_FILE [file join $::quartus(qip_path) "pll_main.cmp"] +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_NAME "cGxsX21haW4=" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_NAME "cGxsX21haW5fMDAwMg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Ng==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MywzLDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDMwLDIwMDAsMzAwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2NsayxmYWxzZQ==::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll_main" -name VHDL_FILE [file join $::quartus(qip_path) "pll_main.vhd"] +set_global_assignment -library "pll_main" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_main/pll_main_0002.v"] +set_global_assignment -library "pll_main" -name QIP_FILE [file join $::quartus(qip_path) "pll_main/pll_main_0002.qip"] + +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_ENV "mwpim" diff --git a/hardware/system/pll/pll_main.sip b/hardware/system/pll/pll_main.sip new file mode 100644 index 0000000..2f4a067 --- /dev/null +++ b/hardware/system/pll/pll_main.sip @@ -0,0 +1,6 @@ +set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_pll_main" -name SPD_FILE [file join $::quartus(sip_path) "pll_main.spd"] + +set_global_assignment -library "lib_pll_main" -name MISC_FILE [file join $::quartus(sip_path) "pll_main_sim/pll_main.vho"] diff --git a/hardware/system/pll/pll_main.spd b/hardware/system/pll/pll_main.spd new file mode 100644 index 0000000..8edf43d --- /dev/null +++ b/hardware/system/pll/pll_main.spd @@ -0,0 +1,6 @@ + + + + + + diff --git a/hardware/system/pll/pll_main.vhd b/hardware/system/pll/pll_main.vhd new file mode 100644 index 0000000..49eb70f --- /dev/null +++ b/hardware/system/pll/pll_main.vhd @@ -0,0 +1,271 @@ +-- megafunction wizard: %PLL Intel FPGA IP v21.1% +-- GENERATION: XML +-- pll_main.vhd + +-- Generated using ACDS version 21.1 850 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity pll_main is + port ( + refclk : in std_logic := '0'; -- refclk.clk + rst : in std_logic := '0'; -- reset.reset + outclk_0 : out std_logic; -- outclk0.clk + locked : out std_logic -- locked.export + ); +end entity pll_main; + +architecture rtl of pll_main is + component pll_main_0002 is + port ( + refclk : in std_logic := 'X'; -- clk + rst : in std_logic := 'X'; -- reset + outclk_0 : out std_logic; -- clk + locked : out std_logic -- export + ); + end component pll_main_0002; + +begin + + pll_main_inst : component pll_main_0002 + port map ( + refclk => refclk, -- refclk.clk + rst => rst, -- reset.reset + outclk_0 => outclk_0, -- outclk0.clk + locked => locked -- locked.export + ); + +end architecture rtl; -- of pll_main +-- Retrieval info: +-- +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- IPFS_FILES : pll_main.vho +-- RELATED_FILES: pll_main.vhd, pll_main_0002.v diff --git a/hardware/system/pll/pll_main/pll_main_0002.qip b/hardware/system/pll/pll_main/pll_main_0002.qip new file mode 100644 index 0000000..c1e1477 --- /dev/null +++ b/hardware/system/pll/pll_main/pll_main_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_main_0002*|altera_pll:altera_pll_i*|*" + +set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_main_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_main_0002*|altera_pll:altera_pll_i*|*" diff --git a/hardware/system/pll/pll_main/pll_main_0002.v b/hardware/system/pll/pll_main/pll_main_0002.v new file mode 100644 index 0000000..b03fce1 --- /dev/null +++ b/hardware/system/pll/pll_main/pll_main_0002.v @@ -0,0 +1,87 @@ +`timescale 1ns/10ps +module pll_main_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("false"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(1), + .output_clock_frequency0("100.000000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/hardware/system/pll/pll_main_sim.f b/hardware/system/pll/pll_main_sim.f new file mode 100644 index 0000000..bd7f7e5 --- /dev/null +++ b/hardware/system/pll/pll_main_sim.f @@ -0,0 +1 @@ +pll_main_sim/pll_main.vho diff --git a/hardware/system/pll/pll_main_sim/aldec/rivierapro_setup.tcl b/hardware/system/pll/pll_main_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..66be505 --- /dev/null +++ b/hardware/system/pll/pll_main_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,284 @@ + +# (C) 2001-2022 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 21.1 850 linux 2022.08.29.18:38:18 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# pll_main +# +# Altera recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Altera simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR