Initial commit
This commit is contained in:
muellerlu
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###############################################################################
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#
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# Actual Synthesis Script
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#
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# This script does the actual synthesis
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#
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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#
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# Revision:
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# 3/7/01 RU Initial Sript
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#
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#
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###############################################################################
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# ==============================================
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# Setup Design Parameters
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source ../bin/design_spec.dc
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# ==============================================
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# Setup Libraries
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source ../bin/lib_spec.dc
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# ==============================================
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# Setup File IO
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set junk_file /dev/null
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append log_file ../log/$active_design "_cmp.log"
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append pre_comp_db_file ../out/$design_name "_pre.db"
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append post_comp_db_file ../out/$design_name ".db"
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append post_syn_verilog_file ../out/$design_name "_ps.v"
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sh rm -f $log_file
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# ==============================================
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# Setup Misc Variables
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set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
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# Turn off automatic wire load selection, as this always (WHY ???) defaults to "zero_load"
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#set auto_wire_load_selection false
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# ==============================================
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# Read Design
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echo "+++++++++ Reading Design ..." >> $log_file
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read_file $pre_comp_db_file >> $log_file
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# ==============================================
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# Operating conditions
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echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
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current_design $design_name
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set_operating_conditions WORST >> $log_file
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#set_wire_load_mode enclosed >> $log_file
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set_wire_load_mode top >> $log_file
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set_wire_load_model -name suggested_40K >> $log_file
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# ==============================================
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# Setup Clocks and Resets
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echo "+++++++++ Setting up Clocks ..." >> $log_file
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set_drive 0 [find port {*clk_i}]
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# !!! Phy Clock !!!
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set clock_period2 16
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create_clock -period $clock_period2 phy_clk
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set_clock_skew -uncertainty 0.5 phy_clk
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set_clock_transition 0.9 phy_clk
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set_dont_touch_network phy_clk
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# !!! WISHBONE Clock !!!
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set clock_period 5
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create_clock -period $clock_period clk_i
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set_clock_skew -uncertainty 0.1 clk_i
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set_clock_transition 0.5 clk_i
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set_dont_touch_network clk_i
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# !!! Reset !!!
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set_drive 0 [find port {rst*}]
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set_dont_touch_network [find port {rst*}]
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# ==============================================
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# Setup IOs
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echo "+++++++++ Setting up IOs ..." >> $log_file
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# Need to spell out external IOs
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set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
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set_load 0.2 [all_outputs]
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set_input_delay -max 1 -clock clk_i [all_inputs]
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set_output_delay -max 1 -clock clk_i [all_outputs]
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set_input_delay -max 1 -clock phy_clk [all_inputs]
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set_output_delay -max 1 -clock phy_clk [all_outputs]
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# ==============================================
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# Setup Area Constrains
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set_max_area 0.0
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# ==============================================
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# Force Ultra
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set_ultra_optimization -f
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# ==============================================
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# Compile Design
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echo "+++++++++ Starting Compile ..." >> $log_file
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#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
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compile -map_effort low -area_effort low >> $log_file
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#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
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# ==============================================
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# Write Out the optimized design
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echo "+++++++++ Saving Optimized Design ..." >> $log_file
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write_file -format verilog -output $post_syn_verilog_file
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write_file -hierarchy -format db -output $post_comp_db_file
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# ==============================================
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# Create Some Basic Reports
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echo "+++++++++ Reporting Final Results ..." >> $log_file
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report_timing -nworst 10 >> $log_file
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report_area >> $log_file
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@@ -0,0 +1,26 @@
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###############################################################################
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#
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# Design Specification
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#
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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#
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# Revision:
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# 3/7/01 RU Initial Sript
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#
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#
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###############################################################################
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# ==============================================
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# Setup Design Parameters
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set design_files {usbf_crc5 usbf_crc16 usbf_mem_arb usbf_ep_rf usbf_pa usbf_ep_rf_dummy usbf_pd usbf_rf usbf_utmi_ls usbf_utmi_if usbf_idma usbf_pe usbf_wb usbf_pl usbf_top}
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set design_name usbf_top
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set active_design usbf_top
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# Next Statement defines all clocks and resets in the design
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set special_net {rst_i clk_i phy_clk}
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# Source Directory
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set hdl_src_dir ../../rtl/verilog/
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@@ -0,0 +1,36 @@
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###############################################################################
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#
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# Library Specification
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#
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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#
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# Revision:
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# 3/7/01 RU Initial Sript
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#
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#
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###############################################################################
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# ==============================================
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# Setup Libraries
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set search_path [list $search_path . \
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/tools/dc_libraries/umc/umc_0.18/UMCL18U250D2_2.1/design_compiler/ \
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$hdl_src_dir]
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set snps [getenv "SYNOPSYS"]
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set synthetic_library ""
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append synthetic_library $snps "/libraries/syn/dw01.sldb "
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append synthetic_library $snps "/libraries/syn/dw02.sldb "
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append synthetic_library $snps "/libraries/syn/dw03.sldb "
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append synthetic_library $snps "/libraries/syn/dw04.sldb "
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append synthetic_library $snps "/libraries/syn/dw05.sldb "
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append synthetic_library $snps "/libraries/syn/dw06.sldb "
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append synthetic_library $snps "/libraries/syn/dw07.sldb "
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set target_library { umcl18u250t2_typ.db }
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set link_library ""
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append link_library $target_library " " $synthetic_library
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set symbol_library { umcl18u250t2.sdb }
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@@ -0,0 +1,66 @@
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###############################################################################
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#
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# Pre Synthesis Script
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#
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# This script only reads in the design and saves it in a DB file
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#
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# Author: Rudolf Usselmann
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# rudi@asics.ws
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#
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# Revision:
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# 3/7/01 RU Initial Sript
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#
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#
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###############################################################################
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# ==============================================
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# Setup Design Parameters
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source ../bin/design_spec.dc
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# ==============================================
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# Setup Libraries
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source ../bin/lib_spec.dc
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# ==============================================
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# Setup File IO
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append log_file ../log/$active_design "_pre.log"
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append pre_comp_db_file ../out/$design_name "_pre.db"
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sh rm -f $log_file
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# ==============================================
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# Setup Misc Variables
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set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
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# ==============================================
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# Read Design
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echo "+++++++++ Analyzing all design files ..." >> $log_file
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foreach module $design_files {
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echo "+++++++++ Reading: $module" >> $log_file
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echo +++++++++ Reading: $module
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set module_file_name ""
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append module_file_name $module ".v"
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analyze -f verilog $module_file_name >> $log_file
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elaborate $module >> $log_file
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}
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set current_design $active_design
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echo "+++++++++ Linking Design ..." >> $log_file
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link >> $log_file
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echo "+++++++++ Uniquifying Design ..." >> $log_file
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uniquify >> $log_file
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echo "+++++++++ Checking Design ..." >> $log_file
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check_design >> $log_file
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# ==============================================
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# Save Design
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echo "+++++++++ Saving Design ..." >> $log_file
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write_file -hierarchy -format db -output $pre_comp_db_file
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