Initial commit
This commit is contained in:
muellerlu
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// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Bomin Kim
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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`timescale 1ns/1ns
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module alu_tb();
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// Local Signals
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logic[2:0] aluOp;
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logic aluNegAr;
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logic aluBypass;
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logic[31:0] op1;
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logic[31:0] op2;
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logic[31:0] result;
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logic eqFlag;
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// Toplevel instance (DUT)
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alu u_alu (
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.aluOp(aluOp),
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.aluNegAr(aluNegAr),
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.aluBypass(aluBypass),
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.op1(op1),
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.op2(op2),
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.result(result),
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.eqFlag(eqFlag)
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);
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// list of aluOp
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localparam logic[2:0] f3add = 3'b000;
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localparam logic[2:0] f3sl = 3'b001;
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localparam logic[2:0] f3slt = 3'b010;
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localparam logic[2:0] f3sltU = 3'b011;
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localparam logic[2:0] f3xor = 3'b100;
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localparam logic[2:0] f3sr = 3'b101;
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localparam logic[2:0] f3or = 3'b110;
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localparam logic[2:0] f3and = 3'b111;
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// Initialize and run simulation
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initial begin
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dumpWave("wave.vcd");
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// Initialize inputs
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aluOp = 0;
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aluNegAr = 0;
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aluBypass = 0;
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op1 = 0;
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op2 = 0;
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#10
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// Set op1 and op2
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op1 = 32'hDEAD_BEEF; op2 = 32'h0000_0001; #70
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$display("\nTime = %0dns \t : op1 = %h, op2 = %h", $time, op1, op2);
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$display("\nTime = %0dns \t : Is op1 and op2 equal?; eqFlag = %d", $time, eqFlag);
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aluBypass = 1; #70
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$display("\nTime = %0dns \t : AluBypass is set; result = %h", $time, result);
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aluBypass = 0; aluOp = f3add; #70
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$display("\nTime = %0dns \t : Alu operates addition; result = %h", $time, result);
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aluNegAr = 1; #70
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$display("\nTime = %0dns \t : Alu operates subtraction; result = %h", $time, result);
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aluNegAr = 0; aluOp = f3sl; #70
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$display("\nTime = %0dns \t : Alu operates shift left; result = %h", $time, result);
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aluOp = f3slt; #70
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$display("\nTime = %0dns \t : Alu operates set less than; result = %h", $time, result);
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aluOp = f3sltU; #70
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$display("\nTime = %0dns \t : Alu operates set less than (unsigned); result = %h", $time, result);
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aluOp = f3xor; #70
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$display("\nTime = %0dns \t : Alu operates bit-wise XOR; result = %h", $time, result);
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aluOp = f3sr; aluNegAr = 1; #70
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$display("\nTime = %0dns \t : Alu operates arithmetic right shift; result = %h", $time, result);
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aluNegAr = 0; #70
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$display("\nTime = %0dns \t : Alu operates logical right shift; result = %h", $time, result);
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aluOp = f3or; #70
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$display("\nTime = %0dns \t : Alu operates bit-wise OR; result = %h", $time, result);
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aluOp = f3and; #70
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$display("\nTime = %0dns \t : Alu operates bit-wise AND; result = %h", $time, result);
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$finish;
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end
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// Wave Dump Helper Task
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task dumpWave(string fileName);
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// Open wave file and dump all signals (2D arrays not included)
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$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
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$dumpfile(fileName);
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$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "alu_tb");
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$dumpvars(0, alu_tb);
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endtask: dumpWave
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endmodule
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@@ -0,0 +1,164 @@
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// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Hussein Elzomor
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// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 H.Elzomor Renamed file and module from soc_tb to cpu_tb
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// *********************************************************************************************
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// `define fibonacci
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// `define helloWorld
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// `define primeFactors
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`timescale 1ns/1ns
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module cpu_tb ();
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// local signals
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logic[7:0] led;
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logic[6:0] btn;
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logic reset;
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logic clk;
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// Toplevel instance (DUT)
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cpu u_cpu (
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.led(led),
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.btn(btn),
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.clk_25mhz(clk)
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);
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// Tie reset signal to the reset button
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assign btn[0] = reset;
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// Clock generation
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always #20 clk = ~clk;
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// Initialize and run simulation
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initial begin
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dumpWave("wave.vcd");
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`ifdef fibonacci
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loadMem("fibonacci.hex");
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`elsif helloWorld
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loadMem("helloWorld.hex");
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`elsif primeFactors
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loadMem("primeFactors.hex");
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`endif
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clk = 0;
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$display("\nTime = %0dns \t : Resetting the CPU", $time);
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reset = 0; #100;
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$display("\nTime = %0dns \t : Reset released", $time);
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reset = 1; #500000;
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$finish;
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end
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// Fibonacci Program Monitor
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`ifdef fibonacci
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localparam int fibonacciStartLoc = 2027;
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localparam int fibonacciLengthInWords = 10;
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always_comb begin: Monitor_Fibonacci_Series_Calculation
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$display("\nTime =%5dns\t\t\t Hex \t Dec", $time);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+0, u_cpu.theMem.RAM[fibonacciStartLoc+0], u_cpu.theMem.RAM[fibonacciStartLoc+0]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+1, u_cpu.theMem.RAM[fibonacciStartLoc+1], u_cpu.theMem.RAM[fibonacciStartLoc+1]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+2, u_cpu.theMem.RAM[fibonacciStartLoc+2], u_cpu.theMem.RAM[fibonacciStartLoc+2]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+3, u_cpu.theMem.RAM[fibonacciStartLoc+3], u_cpu.theMem.RAM[fibonacciStartLoc+3]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+4, u_cpu.theMem.RAM[fibonacciStartLoc+4], u_cpu.theMem.RAM[fibonacciStartLoc+4]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+5, u_cpu.theMem.RAM[fibonacciStartLoc+5], u_cpu.theMem.RAM[fibonacciStartLoc+5]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+6, u_cpu.theMem.RAM[fibonacciStartLoc+6], u_cpu.theMem.RAM[fibonacciStartLoc+6]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+7, u_cpu.theMem.RAM[fibonacciStartLoc+7], u_cpu.theMem.RAM[fibonacciStartLoc+7]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+8, u_cpu.theMem.RAM[fibonacciStartLoc+8], u_cpu.theMem.RAM[fibonacciStartLoc+8]);
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$display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+9, u_cpu.theMem.RAM[fibonacciStartLoc+9], u_cpu.theMem.RAM[fibonacciStartLoc+9]);
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$display("");
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end
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// Hello World Program Monitor
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`elsif helloWorld
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localparam int helloWorldStartLoc = 1024;
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localparam int helloWorldLengthInWords = 4;
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always_comb begin: Monitor_Hello_World_Printing
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$display("\nTime =%5dns\t\t Hex \t\t ASCII", $time);
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$display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+0, u_cpu.theMem.RAM[helloWorldStartLoc+0], u_cpu.theMem.RAM[helloWorldStartLoc+0]);
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$display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+1, u_cpu.theMem.RAM[helloWorldStartLoc+1], u_cpu.theMem.RAM[helloWorldStartLoc+1]);
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$display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+2, u_cpu.theMem.RAM[helloWorldStartLoc+2], u_cpu.theMem.RAM[helloWorldStartLoc+2]);
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$display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+3, u_cpu.theMem.RAM[helloWorldStartLoc+3], u_cpu.theMem.RAM[helloWorldStartLoc+3]);
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$display("");
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end
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// Prime Factors Program Monitor
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`elsif primeFactors
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localparam int primeNumberReg = 16;
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always_comb begin: Monitor_Factorization_Number
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if(u_cpu.theRegisters.registers[primeNumberReg] > 1)
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$display("\nTime =%5dns \t : Register [%0d] updated - Finding the prime factors of %0d", $time,primeNumberReg, u_cpu.theRegisters.registers[primeNumberReg]);
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end
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localparam int primeFactorsReg = 17;
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always_comb begin: Monitor_Prime_Number
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if(u_cpu.theRegisters.registers[primeFactorsReg] > 1)
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$display("Time =%5dns \t : Register [%0d] updated - %0d is a prime factor", $time,primeFactorsReg, u_cpu.theRegisters.registers[primeFactorsReg]);
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end
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`endif
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// Wave Dump Helper Task
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int i;
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task dumpWave(string fileName);
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// Open wave file and dump all signals (2D arrays not included)
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$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
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$dumpfile(fileName);
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$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "cpu_tb");
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$dumpvars(0, cpu_tb);
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// Dump Memory in wave file
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$display("\nTime = %0dns \t : Dumping Memory in wave file", $time);
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for (i = 0; i < 100; i++) begin $dumpvars(0, cpu_tb.u_cpu.theMem.RAM[i]); end // A part of the Instruction Memory
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for (i = 1024; i < 1124; i++) begin $dumpvars(0, cpu_tb.u_cpu.theMem.RAM[i]); end // A part of the Data Memory
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for (i = 1968; i < 2048; i++) begin $dumpvars(0, cpu_tb.u_cpu.theMem.RAM[i]); end // A part of the Stack
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// Dump registers in wave file
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$display("\nTime = %0dns \t : Dumping Registers in wave file", $time);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[1]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[2]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[3]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[4]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[5]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[6]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[7]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[8]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[9]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[10]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[11]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[12]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[13]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[14]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[15]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[16]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[17]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[18]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[19]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[20]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[21]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[22]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[23]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[24]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[25]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[26]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[27]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[28]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[29]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[30]);
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$dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[31]);
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endtask: dumpWave
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// Load hex file into memory
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task loadMem (string fileName);
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$display("\nTime = %0dns \t : Loading '%s' into Memory", $time, fileName);
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$readmemh(fileName, cpu_tb.u_cpu.theMem.RAM);
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endtask: loadMem
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endmodule
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@@ -0,0 +1,150 @@
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// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
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// Created : 15.Oct.2025 by Hussein Elzomor
|
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// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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`timescale 1ns/1ns
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module decoder_tb ();
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// local Parameters
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localparam MEM_SIZE = 37;
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localparam REG_FILE_SIZE = 32;
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// local signals
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logic clk;
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int counter;
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logic[31:0] mem [MEM_SIZE-1:0];
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logic[31:0] regFile [REG_FILE_SIZE-1:0];
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// PC
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logic[31:0] CurrentPC;
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logic[31:0] JumpOrBranchPC;
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logic JumpOrBranch;
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logic[31:0] NextPC;
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// Memory
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logic[31:0] DAddr;
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logic[31:0] WData;
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logic[31:0] RData;
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logic[31:0] Instruction;
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logic WrMem;
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logic[1:0] DWidth;
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// Register File;
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logic[4:0] Rs1;
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logic[4:0] Rs2;
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logic[4:0] Rd;
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logic[31:0] RRs1;
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logic[31:0] RRs2;
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logic[31:0] WRd;
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logic WrReg;
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// Protection
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logic Illegal;
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// Toplevel instance (DUT)
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decoder u_decoder (
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// PC
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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// Memory
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.DAddr(DAddr),
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.WData(WData),
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.RData(RData),
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.Instruction(Instruction),
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.WrMem(WrMem),
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.DWidth(DWidth),
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// Register File
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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// Protection
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.Illegal(Illegal)
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);
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// Clock generation
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always begin
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clk = ~clk; #1;
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end
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// Load a new instruction every cycle
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always_ff @(posedge clk) begin: increment_instruction_and_print_info
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if (counter < MEM_SIZE) begin
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if (counter > 0) printInfo();
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Instruction = mem[counter++];
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end
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end
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// Return the value of the RegFile
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always_comb begin: reg_file_assignment
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RRs1 = regFile[Rs1];
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RRs2 = regFile[Rs2];
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end
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// Initialize and run simulation
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initial begin
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dumpWave("wave.vcd");
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loadMem("decoder.hex");
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clk = 1;
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counter = 0;
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CurrentPC = 32'hdeadbeef;
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RData = 32'hbeefdead;
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for(int i=0; i<REG_FILE_SIZE; i++) begin
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regFile[i] = i;
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end
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while (counter < MEM_SIZE) #1;
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printInfo();
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#1 $finish;
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end
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// Functions
|
||||
// Wave Dump Helper Task
|
||||
task dumpWave(string fileName);
|
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// Open wave file and dump all signals (2D arrays not included)
|
||||
$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
|
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$dumpfile(fileName);
|
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$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "decoder_tb");
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$dumpvars(0, decoder_tb);
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endtask: dumpWave
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||||
// Load hex file into memory
|
||||
task loadMem (string fileName);
|
||||
$display("\nTime = %0dns \t : Loading '%s' into Memory", $time, fileName);
|
||||
$readmemh(fileName, mem);
|
||||
endtask: loadMem
|
||||
|
||||
// Print decoder signals
|
||||
task printInfo();
|
||||
$displayh("\n(cycle %0d) Decoder (I/O) \tDecoder (Internal Signals) \tALU" , counter );
|
||||
$displayh(" -------------------------- \t--------------------------------------------- \t---------------------" );
|
||||
$displayh(" CurrentPC : 0x%h OpCode : 0b%b aluOp : 0b%b" , CurrentPC , u_decoder.theOp , u_decoder.aluOp );
|
||||
$displayh(" JumpOrBranchPC: 0x%h theFunct3: 0b%b aluNegAr : 0b%b" , JumpOrBranchPC, u_decoder.theFunct3, u_decoder.aluNegAr );
|
||||
$displayh(" JumpOrBranch : 0b%b \ttheFunct7: 0b%b aluBypass: 0b%b", JumpOrBranch , u_decoder.theFunct7, u_decoder.aluBypass);
|
||||
$displayh(" DAddr : 0x%h i_imm : 0b%b op1 : 0x%h" , DAddr , u_decoder.i_imm , u_decoder.op1 );
|
||||
$displayh(" WData : 0x%h s_imm : 0b%b op2 : 0x%h" , WData , u_decoder.s_imm , u_decoder.op2 );
|
||||
$displayh(" RData : 0x%h b_imm : 0b%b result : 0x%h" , RData , u_decoder.b_imm , u_decoder.result );
|
||||
$displayh(" Instruction : 0x%h u_imm : 0b%b eqFlag : 0b%b" , Instruction , u_decoder.u_imm , u_decoder.eqFlag );
|
||||
$displayh(" WrMem : 0b%b \tj_imm : 0b%b" , WrMem , u_decoder.j_imm );
|
||||
$displayh(" DWidth : 0b%b" , DWidth );
|
||||
$displayh(" Rs1 : %0d " , Rs1 );
|
||||
$displayh(" Rs2 : %0d " , Rs2 );
|
||||
$displayh(" Rd : 0x%h" , Rd );
|
||||
$displayh(" RRs1 : %0d " , RRs1 );
|
||||
$displayh(" RRs2 : %0d " , RRs2 );
|
||||
$displayh(" WRd : 0x%h" , WRd );
|
||||
$displayh(" WrReg : 0b%b" , WrReg );
|
||||
$displayh(" Illegal : 0b%b" , Illegal );
|
||||
endtask: printInfo
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,238 @@
|
||||
// *********************************************************************************************
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 20.Oct.2025 by Aliakbar Merchant
|
||||
// Last Modified : 24.Oct.2025 by Aliakbar Merchant [commit 89a5087]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
|
||||
`timescale 1ns/1ns
|
||||
|
||||
module main_mem_tb ();
|
||||
|
||||
// local Parameters
|
||||
localparam string MEM_INIT_FILE = "main_mem.hex";
|
||||
// Helpers for addressing width
|
||||
localparam logic[1:0] _byte = 2'b00; // byte: 8 bits
|
||||
localparam logic[1:0] _half = 2'b01; // half: 16 bits
|
||||
localparam logic[1:0] _word = 2'b10; // word: 32 bits
|
||||
|
||||
// Local Signals
|
||||
// clk and reset
|
||||
logic clk;
|
||||
logic reset;
|
||||
// Memory
|
||||
logic[31:0] DAddr;
|
||||
logic[31:0] IAddr;
|
||||
logic[31:0] DWData;
|
||||
logic[31:0] DRData;
|
||||
logic[31:0] IRData;
|
||||
logic DWE;
|
||||
logic[1:0] DWidth;
|
||||
// Helpers for display results purpose
|
||||
logic[31:0] value_at_0;
|
||||
logic[31:0] value_at_1;
|
||||
logic[31:0] value_at_2;
|
||||
logic[31:0] value_at_3;
|
||||
logic[31:0] value_at_1024;
|
||||
logic[31:0] value_at_1025;
|
||||
logic[31:0] value_at_1026;
|
||||
logic[31:0] value_at_1027;
|
||||
|
||||
// Toplevel instance (DUT)
|
||||
main_mem u_main_mem (
|
||||
.clk (clk ),
|
||||
.reset (reset ),
|
||||
.DAddr (DAddr ),
|
||||
.IAddr (IAddr ),
|
||||
.DWData (DWData ),
|
||||
.DRData (DRData ),
|
||||
.IRData (IRData ),
|
||||
.DWE (DWE ),
|
||||
.DWidth (DWidth )
|
||||
);
|
||||
|
||||
// Clock generation
|
||||
always #1 clk = ~clk;
|
||||
|
||||
// Initialize and run simulation
|
||||
initial begin
|
||||
loadMem(MEM_INIT_FILE);
|
||||
value_at_0 = main_mem_tb.u_main_mem.RAM[0];
|
||||
value_at_1 = main_mem_tb.u_main_mem.RAM[1];
|
||||
value_at_2 = main_mem_tb.u_main_mem.RAM[2];
|
||||
value_at_3 = main_mem_tb.u_main_mem.RAM[3];
|
||||
value_at_1024 = main_mem_tb.u_main_mem.RAM[1024];
|
||||
value_at_1025 = main_mem_tb.u_main_mem.RAM[1025];
|
||||
value_at_1026 = main_mem_tb.u_main_mem.RAM[1026];
|
||||
value_at_1027 = main_mem_tb.u_main_mem.RAM[1027];
|
||||
clk = 0;
|
||||
DAddr = 32'd4096;
|
||||
IAddr = 0;
|
||||
DWData = 0;
|
||||
DWidth = 0;
|
||||
reset = 1; DWE=1; #7;
|
||||
DWE = 0;
|
||||
reset = 0; #2;
|
||||
test_scenario1(); #30;
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Test scenario 1
|
||||
task test_scenario1();
|
||||
fork
|
||||
read_inst_mem(15);
|
||||
display_inst_read_results();
|
||||
write_data_mem(4096);
|
||||
join
|
||||
display_write_results();
|
||||
fork
|
||||
display_read_results();
|
||||
read_data_mem(4096);
|
||||
join
|
||||
endtask: test_scenario1
|
||||
|
||||
// Intruction memory read transactions and results display
|
||||
task read_inst_mem(int unsigned n = 1);
|
||||
repeat(n) begin
|
||||
cycles_pe(1);
|
||||
IAddr = IAddr+4;
|
||||
end
|
||||
endtask:read_inst_mem
|
||||
|
||||
task display_inst_read_results();
|
||||
$display("\n----------------------------------------------------------------------------------" );
|
||||
$display("Instruction MEMORY READ RESULTS" );
|
||||
$display("15 instruction are read by testbench starting at adrress 0x0000 i.e at (RAM[0]) but only 4 displyed for simplicity" );
|
||||
$display("----------------------------------------------------------------------------------" );
|
||||
|
||||
cycles_pe(2);
|
||||
$display("Time = %0dns \t : IAddr = 0x0000(RAM[0]): Expected value = 0x%h Actual Value at IRData: 0x%h" , $time, value_at_0, IRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : IAddr = 0x0004(RAM[1]): Expected value = 0x%h Actual Value at IRData: 0x%h" , $time, value_at_1, IRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : IAddr = 0x0008(RAM[2]): Expected value = 0x%h Actual Value at IRData: 0x%h" , $time, value_at_2, IRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : IAddr = 0x000c(RAM[3]): Expected value = 0x%h Actual Value at IRData: 0x%h" , $time, value_at_3, IRData );
|
||||
endtask:display_inst_read_results
|
||||
|
||||
// Data memory write transaction and results display
|
||||
task write_data_mem(logic [31:0] daddr_init=32'd4096);
|
||||
cycles_pe(1);
|
||||
DWE = 1;
|
||||
DWidth = 0;
|
||||
DAddr = daddr_init+0;
|
||||
DWData = 32'hDEADBEEF;
|
||||
cycles_pe(1);
|
||||
DWE = 1;
|
||||
DWidth = 1;
|
||||
DAddr = daddr_init+4;
|
||||
DWData = 32'hDEADBEEF;
|
||||
cycles_pe(1);
|
||||
DWE = 1;
|
||||
DWidth = 2;
|
||||
DAddr = daddr_init+8;
|
||||
DWData = 32'hDEADBEEF;
|
||||
cycles_pe(1);
|
||||
DWE = 1;
|
||||
DWidth = 3;
|
||||
DAddr = daddr_init+12;
|
||||
DWData = 32'hDEADBEEF;
|
||||
cycles_pe(1);
|
||||
DWE = 0;
|
||||
endtask:write_data_mem
|
||||
|
||||
task display_write_results();
|
||||
$display("\n----------------------------------------------------------------------------------" );
|
||||
$display("DATA MEMORY WRITE RESULTS" );
|
||||
$display("4 Write transaction are being done by testbench starting at adrress 0x1000 i.e at (RAM[1024]) with all 4 combination of DWidth" );
|
||||
$display("Data written is always 0xDEADBEEF i.e DWData = DEADBEEF" );
|
||||
$display("----------------------------------------------------------------------------------" );
|
||||
|
||||
$display("Time = %0dns \t : DWidth = 0 DAddr = 0x1000(RAM[1024]): Start value at RAM[1024] = 0x%h Expected value at RAM[1024]= 0xef%h Actual Value at RAM[1024]: 0x%h" , $time, value_at_1024,value_at_1024[23:0], getMem(1024) );
|
||||
$display("Time = %0dns \t : DWidth = 1 DAddr = 0x1004(RAM[1025]): Start value at RAM[1025] = 0x%h Expected value at RAM[1025]= 0xbeef%h Actual Value at RAM[1025]: 0x%h" , $time, value_at_1025,value_at_1025[15:0], getMem(1025) );
|
||||
$display("Time = %0dns \t : DWidth = 2 DAddr = 0x1008(RAM[1026]): Start value at RAM[1026] = 0x%h Expected value at RAM[1026]= 0xdeadbeef Actual Value at RAM[1026]: 0x%h" , $time, value_at_1026, getMem(1026) );
|
||||
$display("Time = %0dns \t : DWidth = 3 DAddr = 0x100c(RAM[1027]): Start value at RAM[1027] = 0x%h Expected value at RAM[1027]= 0x%h Actual Value at RAM[1027]: 0x%h" , $time, value_at_1027,value_at_1027, getMem(1027) );
|
||||
endtask:display_write_results
|
||||
|
||||
// Data Memory read transaction and results display
|
||||
task read_data_mem(logic [31:0] daddr_init=32'd4096);
|
||||
cycles_pe(1);
|
||||
DWidth = 0;
|
||||
DAddr = daddr_init+0;
|
||||
cycles_pe(1);
|
||||
DWidth = 1;
|
||||
DAddr = daddr_init+4;
|
||||
cycles_pe(1);
|
||||
DWidth = 2;
|
||||
DAddr = daddr_init+8;
|
||||
cycles_pe(1);
|
||||
DWidth = 3;
|
||||
DAddr = daddr_init+12;
|
||||
cycles_pe(1);
|
||||
DWidth = 2;
|
||||
DAddr = daddr_init+0;
|
||||
cycles_pe(1);
|
||||
DWidth = 2;
|
||||
DAddr = daddr_init+4;
|
||||
cycles_pe(1);
|
||||
DWidth = 2;
|
||||
DAddr = daddr_init+8;
|
||||
cycles_pe(1);
|
||||
DWidth = 2;
|
||||
DAddr = daddr_init+12;
|
||||
endtask:read_data_mem
|
||||
|
||||
task display_read_results();
|
||||
$display("\n----------------------------------------------------------------------------------" );
|
||||
$display("DATA MEMORY READ RESULTS" );
|
||||
$display("8 Read transaction are being done by testbench starting at adrress 0x1000 i.e at (RAM[1024])" );
|
||||
$display("----------------------------------------------------------------------------------" );
|
||||
|
||||
cycles_pe(2);
|
||||
$display("Time = %0dns \t : DWidth = 0 DAddr = 0x1000(RAM[1024]): Expected value = 0x000000ef Actual Value at DRData: 0x%h" , $time, DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 1 DAddr = 0x1004(RAM[1025]): Expected value = 0x0000beef Actual Value at DRData: 0x%h" , $time, DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 2 DAddr = 0x1008(RAM[1026]): Expected value = 0xdeadbeef Actual Value at DRData: 0x%h" , $time, DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 3 DAddr = 0x100c(RAM[1027]): Expected value = 0xdeadbeef Actual Value at DRData: 0x%h" , $time, DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 2 DAddr = 0x1000(RAM[1024]): Expected value = 0xef%h Actual Value at DRData: 0x%h" , $time, value_at_1024[23:0], DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 2 DAddr = 0x1004(RAM[1025]): Expected value = 0xbeef%h Actual Value at DRData: 0x%h" , $time, value_at_1025[15:0], DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 2 DAddr = 0x1008(RAM[1026]): Expected value = 0xdeadbeef Actual Value at DRData: 0x%h" , $time, DRData );
|
||||
cycles_pe(1);
|
||||
$display("Time = %0dns \t : DWidth = 2 DAddr = 0x100c(RAM[1027]): Expected value = 0x%h Actual Value at DRData: 0x%h" , $time, value_at_1027, DRData );
|
||||
endtask:display_read_results
|
||||
|
||||
|
||||
// Helper tasks
|
||||
// Memory
|
||||
function int getMem(int location);
|
||||
getMem = u_main_mem.RAM[location];
|
||||
endfunction: getMem
|
||||
|
||||
task cycles_pe(int unsigned N = 1);
|
||||
repeat(N) @(posedge clk);
|
||||
endtask: cycles_pe
|
||||
|
||||
task cycles_ne(int unsigned N = 1);
|
||||
repeat(N) @(negedge clk);
|
||||
endtask: cycles_ne
|
||||
|
||||
// Load hex file into memory
|
||||
task loadMem (string fileName);
|
||||
$display("\nTime = %0dns \t : Loading '%s' into Memory", $time, fileName);
|
||||
$readmemh(fileName, main_mem_tb.u_main_mem.RAM);
|
||||
endtask: loadMem
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,68 @@
|
||||
// *********************************************************************************************
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 15.Oct.2025 by Bomin Kim
|
||||
// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
|
||||
`timescale 1ns/1ns
|
||||
|
||||
module pc_tb ();
|
||||
|
||||
// Local Signals
|
||||
logic[31:0] CurrentPC;
|
||||
logic[31:0] JumpOrBranchPC;
|
||||
logic JumpOrBranch;
|
||||
logic[31:0] NextPC;
|
||||
logic reset;
|
||||
logic clk;
|
||||
|
||||
// Toplevel instance (DUT)
|
||||
pc u_pc (
|
||||
.CurrentPC(CurrentPC),
|
||||
.JumpOrBranchPC(JumpOrBranchPC),
|
||||
.JumpOrBranch(JumpOrBranch),
|
||||
.NextPC(NextPC),
|
||||
.reset(reset),
|
||||
.clk(clk)
|
||||
);
|
||||
|
||||
// Clock generation
|
||||
always #20 clk = ~clk;
|
||||
|
||||
// Initialization and run simulation
|
||||
initial begin
|
||||
dumpWave("wave.vcd");
|
||||
clk = 0;
|
||||
JumpOrBranchPC = 32'h8;
|
||||
JumpOrBranch = 0;
|
||||
reset = 0; #100;
|
||||
reset = 1; #100;
|
||||
reset = 0; #490;
|
||||
JumpOrBranch = 1; #60;
|
||||
JumpOrBranch = 0; #500;
|
||||
$finish;
|
||||
end
|
||||
|
||||
// NextPC Monitor
|
||||
initial begin
|
||||
$monitor("time=%0t clk=%b reset=%b JumpOrBranch=%0h CurrentPC=%0h NextPC=%0h", $time, clk, reset, JumpOrBranch, CurrentPC, NextPC);
|
||||
end
|
||||
|
||||
// Wave Dump Helper Task
|
||||
task dumpWave(string fileName);
|
||||
// Open wave file and dump all signals (2D arrays not included)
|
||||
$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
|
||||
$dumpfile(fileName);
|
||||
$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "pc_tb");
|
||||
$dumpvars(0, pc_tb);
|
||||
endtask: dumpWave
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,137 @@
|
||||
// *********************************************************************************************
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 15.Oct.2025 by Bomin Kim
|
||||
// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
|
||||
`timescale 1ns/1ns
|
||||
|
||||
module reg_file_tb ();
|
||||
|
||||
// Local Signals
|
||||
logic[4:0] Rs1;
|
||||
logic[4:0] Rs2;
|
||||
logic[4:0] Rd;
|
||||
logic[31:0] RRs1;
|
||||
logic[31:0] RRs2;
|
||||
logic[31:0] WRd;
|
||||
logic WrReg;
|
||||
logic reset;
|
||||
logic clk;
|
||||
|
||||
// Toplevel instance (DUT)
|
||||
reg_file u_reg_file (
|
||||
.Rs1(Rs1),
|
||||
.Rs2(Rs2),
|
||||
.Rd(Rd),
|
||||
.RRs1(RRs1),
|
||||
.RRs2(RRs2),
|
||||
.WRd(WRd),
|
||||
.WrReg(WrReg),
|
||||
.reset(reset),
|
||||
.clk(clk)
|
||||
);
|
||||
|
||||
// Clock generation
|
||||
always #20 clk = ~clk;
|
||||
|
||||
// Initialization and run simulation
|
||||
initial begin
|
||||
dumpWave("wave.vcd");
|
||||
|
||||
// Initialize inputs
|
||||
clk = 0;
|
||||
Rs1 = 0; Rs2 = 0; Rd = 0;
|
||||
WRd = 0; WrReg = 0; // Read
|
||||
reset = 1;
|
||||
|
||||
#50
|
||||
reset = 0;
|
||||
|
||||
#50 // Write 0xDEADBEEF to reg21
|
||||
Rd = 5'd21;
|
||||
WrReg = 1; // Write
|
||||
WRd = 32'hDEADBEEF;
|
||||
#50; WrReg = 0;
|
||||
|
||||
#50
|
||||
Rs1 = 5'd21; // read reg21 into RRs1
|
||||
Rs2 = 5'd0;
|
||||
|
||||
#50 // Write 0x12345678 to reg5
|
||||
Rd = 5'd5;
|
||||
WrReg = 1; // Write
|
||||
WRd = 32'h12345678;
|
||||
#50; WrReg = 0;
|
||||
|
||||
#50
|
||||
Rs1 = 5'd5; // read reg10 into RRs1
|
||||
|
||||
#50
|
||||
Rs1 = 5'd0; // read zero register
|
||||
|
||||
#50
|
||||
Rd = 5'd0; // attempt to write 0xCAFEBABE to zero register
|
||||
WRd = 32'hCAFEBABE;
|
||||
WrReg = 1; // Write
|
||||
#50; WrReg = 0;
|
||||
|
||||
#50
|
||||
Rs1 = 5'd5; // Read from reg5
|
||||
#200
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Wave Dump Helper Task
|
||||
task dumpWave(string fileName);
|
||||
// Open wave file and dump all signals (2D arrays not included)
|
||||
$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
|
||||
$dumpfile(fileName);
|
||||
$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "reg_file_tb");
|
||||
$dumpvars(0, reg_file_tb);
|
||||
|
||||
// Dump registers in wave file
|
||||
$display("\nTime = %0dns \t : Dumping Registers in wave file", $time);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[1]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[2]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[3]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[4]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[5]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[6]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[7]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[8]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[9]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[10]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[11]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[12]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[13]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[14]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[15]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[16]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[17]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[18]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[19]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[20]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[21]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[22]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[23]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[24]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[25]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[26]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[27]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[28]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[29]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[30]);
|
||||
$dumpvars(0, reg_file_tb.u_reg_file.registers[31]);
|
||||
endtask: dumpWave
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,79 @@
|
||||
# OpenFile ./cpu_tb.sv
|
||||
ls
|
||||
# alu_tb.sv decoder_tb.sv pc_tb.sv transcript
|
||||
# cpu_tb.sv main_mem_tb.sv reg_file_tb.sv work
|
||||
vsim compile.tcl
|
||||
# vsim compile.tcl
|
||||
# Start time: 11:01:25 on Nov 28,2025
|
||||
# ** Error (suppressible): (vsim-19) Failed to access library 'compile' at "compile".
|
||||
# No such file or directory. (errno = ENOENT)
|
||||
# Error loading design
|
||||
# End time: 11:01:25 on Nov 28,2025, Elapsed time: 0:00:00
|
||||
# Errors: 1, Warnings: 0
|
||||
ls
|
||||
# alu_tb.sv decoder_tb.sv pc_tb.sv transcript
|
||||
# cpu_tb.sv main_mem_tb.sv reg_file_tb.sv work
|
||||
cd ..
|
||||
ls
|
||||
# rtl verilator wave_configs
|
||||
cd ..
|
||||
pwd
|
||||
# C:/PhD/RISC-V Design Course Material/RISC-V Desgin Course - Complete Source Code/riscv_in3days-public/hw
|
||||
cd ..
|
||||
ls
|
||||
# README.md doc hw sw
|
||||
cd ..
|
||||
ls
|
||||
# riscv_in3days-public
|
||||
cd ..
|
||||
ls
|
||||
# Course Introduction & Closing - Public.pdf
|
||||
# Day 1
|
||||
# Day 2
|
||||
# Day 3
|
||||
# Day 4
|
||||
# RISC-V Desgin Course - Complete Source Code
|
||||
# References
|
||||
cd ..
|
||||
cd ..
|
||||
la
|
||||
# ambiguous command name "la": label labelframe langOf lappend lassign lattice_edition layout
|
||||
ls
|
||||
# Drivers Program Files (x86) inetpub
|
||||
# DumpStack.log Steam_Community_Markt intelFPGA
|
||||
# Lukas Users intelFPGA_lite
|
||||
# PhD Windows vfcompat.dll
|
||||
# ProcLogs appverifUI.dll
|
||||
# Program Files flexlm
|
||||
pwd
|
||||
# C:/
|
||||
ls
|
||||
# Drivers Program Files (x86) inetpub
|
||||
# DumpStack.log Steam_Community_Markt intelFPGA
|
||||
# Lukas Users intelFPGA_lite
|
||||
# PhD Windows vfcompat.dll
|
||||
# ProcLogs appverifUI.dll
|
||||
# Program Files flexlm
|
||||
cd PhD
|
||||
ls
|
||||
# Code compile.tcl
|
||||
# RISC-V Design Course Material
|
||||
cd RISC-V Design Course Material
|
||||
# wrong # args: should be "cd ?dirName?"
|
||||
ls
|
||||
# Code compile.tcl
|
||||
# RISC-V Design Course Material
|
||||
ls
|
||||
# Code compile.tcl
|
||||
# RISC-V Design Course Material
|
||||
cd RISC-V Design Course Material
|
||||
# wrong # args: should be "cd ?dirName?"
|
||||
ls
|
||||
# Code compile.tcl
|
||||
# RISC-V Design Course Material
|
||||
run compile.tcl
|
||||
# No Design Loaded!
|
||||
compile.tcl
|
||||
# couldn't execute ".\compile.tcl": no such file or directory
|
||||
run compile.tcl
|
||||
# No Design Loaded!
|
||||
@@ -0,0 +1,10 @@
|
||||
m255
|
||||
K4
|
||||
z2
|
||||
13
|
||||
!s112 1.1
|
||||
!i10d 8192
|
||||
!i10e 25
|
||||
!i10f 100
|
||||
cModel Technology
|
||||
dC:/PhD/RISC-V Design Course Material/RISC-V Desgin Course - Complete Source Code/riscv_in3days-public/hw/dv/rtl
|
||||
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Reference in New Issue
Block a user