Initial commit

riscv_rtl/hw/dv/verilator/Makefile

@@ -0,0 +1,78 @@
+export  PRJ_ROOT			= ../../..
+
+
+# directroy containig syrinx application programs
+SWDIR = $(PRJ_ROOT)/sw/risc-v
+DVDIR = $(PRJ_ROOT)/hw/dv
+
+# toplevel syrinx file list
+RTL_FLIST = $(PRJ_ROOT)/hw/file_lists/rtl_flist.f
+TB_FLIST  = $(PRJ_ROOT)/hw/file_lists/tb_flist.f
+
+
+# if we have multiple file list, we combine them here
+FLIST = -f $(RTL_FLIST) -f $(TB_FLIST)
+
+# Default number of simulation cycles
+NCYCLES	?= 500
+
+# Standard boot loader and dummy application to be used if nothing else is specified
+
+PROG ?= $(SWDIR)/hello_world/helloWorld.hex
+
+# top module name
+TOPMODULE = cpu_harness
+
+# NUmber of GCC parallel threads
+COMPILE_THREADS = 32
+
+# Verilator CPU usage, should be adapated to simulation host
+SIM_THREADS 	= 4
+TRACE_THREADS = 1
+
+
+EXTRA_ARGS += --trace-fst --trace-structs --trace-max-array 2048 --trace-threads $(TRACE_THREADS) --threads $(SIM_THREADS)
+EXTRA_ARGS += --clk clk --no-timing
+# EXTRA_ARGS += -O2
+
+# Used by some code constructs
+VDEFS		= +define+SIMULATION
+
+
+
+all: ./obj_dir/V$(TOPMODULE)
+
+wave: wavedump.fst
+	@echo
+	@echo "*** Starting waveform viewer..."
+	$(WAVE_VIEWER) wavedump.fst -s $(DVDIR)/wave_configs/verilator_wave.surf.ron
+
+run:
+	@echo
+	@echo "*** Running simulation..."
+	@./obj_dir/V$(TOPMODULE) $(NCYCLES) $(PROG)
+
+./obj_dir/V$(TOPMODULE): .stamp.verilate
+	@echo
+	@echo "*** Building simulator..."
+	make -C obj_dir -f V$(TOPMODULE).mk V$(TOPMODULE) -j $(COMPILE_THREADS)
+
+.stamp.verilate:  src/tb_$(TOPMODULE).cpp
+	@echo "*** Generating C++ model..."
+	$(VERILATOR) --trace $(EXTRA_ARGS) $(VDEFS) -cc $(FLIST) --top-module $(TOPMODULE) --exe src/tb_$(TOPMODULE).cpp
+	@touch .stamp.verilate
+
+lint:$(VERILOG_SOURCES)
+	$(VERILATOR) --lint-only $(INCLUDES) $(VERILOG_SOURCES) --top-module $(TOPMODULE)
+
+
+paths:
+	@echo $(PRJ_ROOT)/$(APB)
+
+
+
+clean:
+	rm -rf .stamp.*;
+	rm -rf ./obj_dir
+	rm -rf wavedump.fst*
+	rm -rf *.dasm