Initial commit
This commit is contained in:
muellerlu
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Executable
+72
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#########################################################
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# 1_load_design.tcl
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#
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# Description: Load the design input files into
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# Oasys-RTL and set design
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# conditions. Must be run after the
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# init_design.tcl script
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#
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# Usage: source in Oasys-RTL Command prompt
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#
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# Dependencies: init_design.tcl
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# Launched from Oasys-RTL shell
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#
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#########################################################
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set script_dir [file dirname [info script]]
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set ekit_dir [file dirname ${script_dir}]
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#Check if dependent scripts have been loaded
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if {![info exists top_module]} {
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source ${script_dir}/init_design.tcl
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}
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#=======================================================#
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#Load technology libraries (Liberty and LEF)
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#=======================================================#
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# Read Oasys libraries (ODB)
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read_db ${ekit_dir}/libs/nangate_mvt.odb
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foreach vt [list hvt svt lvt] {
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set vtUC [string toupper $vt]
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set lib_cells(${vt}) [get_lib_cells *${vtUC}*]
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if { [sizeof_collection $lib_cells(${vt})] > 0 } {
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create_threshold_voltage_group ${vtUC} -lib_cells $lib_cells($vt)
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}
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}
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report_operating_conditions
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#=======================================================#
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#Config the tolerance level for RTL parser for elobration
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#=======================================================#
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config_tolerance -blackbox true -connection_mismatch true \
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-missing_physical_library true \
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-continue_on_error false
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#=======================================================#
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#Read verilog design files
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#=======================================================#
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if {[file exists ${ekit_dir}/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v]} {
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read_verilog $rtl_list -include $search_path
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}
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#=======================================================#
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#Set design-specific parameters before synthesis
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#=======================================================#
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#Set the max routing layer (defined in 1_init_design.tcl)
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set_max_route_layer $max_route_layer
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#Reset dont_use property on all lib cells
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set_dont_use [get_lib_cell * ] false
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#Specify clock gating options
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set_clock_gating_options -control_point before \
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-minimum_bitwidth 4 -sequential_cell latch
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echo "\n-----------------------------"
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echo "\nDone preparing design for synthesis"
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echo "\n-----------------------------\n"
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Executable
+117
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#########################################################
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# 2_synthesize_optimize.tcl
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#
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# Description: Synthesize and optimize the
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# DEMO CHIP and generate
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# the Oasys-RTL databases.
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#
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# Usage: source in Oasys-RTL Command prompt
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#
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# Dependencies: init_design.tcl
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# 1_read_design.tcl
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# Launched from Oasys-RTL shell
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#
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#########################################################
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#=======================================================#
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#Check Status of Flow and load prior scripts if needed
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#=======================================================#
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set script_dir [file dirname [info script]]
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set ekit_dir [file dirname ${script_dir}]
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#Check if dependent scripts have been loaded
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if {![info exists top_module]} {
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source ${script_dir}/init_design.tcl
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source ${script_dir}/1_read_design.tcl
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}
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#=======================================================#
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#Synthesize the DEMO CHIP RTL core
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#=======================================================#
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if {![file exists ${ekit_dir}/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v]} {
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puts "ERROR: RTL source files from OpenCores.org were not found.\n"
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puts "You can read a design database for a previously optimized design"
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puts "by running the following command:\n"
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puts "read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb\n\n"
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return
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}
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#Perform Synthesis
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synthesize -module ${top_module} -map_to_scan -gate_clock
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set_route_layer_max_usage metal2 0.5
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set_route_layer_max_usage metal3 0.8
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set_route_layer_max_usage metal6 0.8
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write_db ${output_dir}/odb/demo_chip.syn.odb
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#=======================================================#
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##Read constraints (logical and physical)
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#=======================================================#
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read_sdc -verbose $demo_chip_sdc_files
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#read_sdc -verbose constraints/cts_constraints.sdc
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report_design_metrics
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check_timing
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# Create User Path groups
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group_path -name I2R -from [all_inputs]
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group_path -name I2O -from [all_inputs] -to [all_outputs]
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group_path -name R2O -to [all_outputs]
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report_path_groups
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#=======================================================#
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#Optimize for timing
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#=======================================================#
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optimize -virtual
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write_db ${output_dir}/odb/demo_chip.virtual_opt.odb
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report_timing
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report_path_groups
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######################################################################
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# create_chip with appropriate bloackages for IO pads
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######################################################################
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redirect -file ${output_dir}/demo_chip.create_chip.log { create_chip -bottom_clearance 30 -left_clearance 30 -right_clearance 30 -top_clearance 30 -utilization 60 }
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set die [ exec cat ${output_dir}/demo_chip.create_chip.log | grep "create new die" | cut -c46-56 ]
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set core [ expr $die - 30]
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create_blockage -name blk_top -type macro -left 0 -right $die -bottom $core -top $die
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create_blockage -name blk_bottom -type macro -left 0 -right $die -bottom 0 -top 30
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create_blockage -name blk_left -type macro -left 0 -right 30 -bottom 0 -top $die
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create_blockage -name blk_right -type macro -left $core -right $die -bottom 0 -top $die
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#optimize for placement
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optimize -place
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write_db ${output_dir}/odb/demo_chip.placed_opt.odb
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report_timing
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report_path_groups
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echo "\n-------------------------------------"
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echo "\nSynthesis and optimization complete"
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echo "\n-------------------------------------\n"
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#=======================================================#
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#Perform DFT
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#=======================================================#
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if {[info exists dft_flow] && [string match $dft_flow tessent]} {
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puts "INFO::Running oasys Tessent DFT flow"
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source scripts/oasys_tessent_dft.tcl
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echo "\n-------------------------------------"
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echo "\n Tessent DFT complete"
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echo "\n-------------------------------------\n"
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} elseif {[info exists dft_flow] && [string match $dft_flow oasys]} {
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puts "INFO::Running oasys native DFT flow"
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source scripts/oasys_dft.tcl
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report_scan_chains
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echo "\n-------------------------------------"
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echo "\n Oasys DFT complete"
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echo "\n-------------------------------------\n"
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} else {
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puts "\nINFO:: 'dft_flow' variable not set to 'tessent' or 'oasys'."
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puts " skipping DFT flow. 'source' following script to run DFT"
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puts " source ${ekit_dir}/scripts/oasys_dft.tcl"
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puts " source ${ekit_dir}/scripts/oasys_tessent_dft.tcl"
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}
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#exit
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Executable
+32
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#########################################################
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# 3_export_design.tcl
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#
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# Description: Export the design data
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#
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# Usage: source in Oasys-RTL Command prompt
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#
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# Dependencies: init_design.tcl
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# 1_load_design.tcl
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# 2_synthesize_optimize.tcl
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# Launched from Oasys-RTL shell after
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# synthesis and optimization
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#
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#########################################################
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#Check if dependent scripts have been loaded
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if {![info exists top_module]} {
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source scripts/init_design.tcl
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}
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# Write results
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write_db ${output_dir}/odb/demo_chip.oasys_final.odb
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write_verilog ${output_dir}/demo_chip.oasys_final.v
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write_sdc ${output_dir}/demo_chip.oasys_final.sdc
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write_def ${output_dir}/demo_chip.def
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write_stil ${output_dir}/demo_chip.stil
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write_ctl ${output_dir}/demo_chip.ctl
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echo "\n-----------------------------"
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echo "\nDesign data exported to output dir."
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echo "\n-----------------------------\n"
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Executable
+37
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###POWER PLANNING####
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##Make PG rails and stripes and connect macros to the power pins##
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create_supply_net -net_name VDD -power_net true
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create_supply_net -net_name VSS -power_net false
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connect_supply_net VDD -pins [get_pins *vdd* ]
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connect_supply_net VSS -pins [get_pins *gnd* ]
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## Adding Power Structure
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remove_routing -route_types pre_route
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create_pg_rings -partitions "demo_chip" -nets "VDD VSS" -window false -layers { metal9 metal10 } -widths { 45000a 50000a } -step 32000a -spacing 15000a -offset { 165000a 165000a 165000a 165000a } -keep_pattern all -bridge_pattern single -ignore_blockages { placement } -check_drc { all } -measure_from edge -corner_style concentric -insert_vias true -location auto
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create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal10 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction vertical -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all }
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create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal9 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction horizontal -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all }
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insert_pg_vias -nets {VDD VSS} -layers {metal9 metal10} -extend true -from_type stripe -to_type ring
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insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal10}
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create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal4 -widths { 40000a 40000a } -step 500000a -spacing 20000a -direction vertical -offset { 800000a 800000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all }
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insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal4} -extend true
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insert_pg_vias -nets {VDD VSS} -from_type ring -to_type stripe -layers {metal9 metal4} -extend true
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create_pg_rails -partitions "demo_chip" -nets "VDD VSS" -window false -sites "FreePDK45_38x28_10R_NP_162NW_34O" -ignore_blockages { none }
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insert_pg_vias -from_type stripe -to_type rail -layers {metal1 metal4}
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insert_pg_vias -nets {VDD VSS} -layers {metal6 metal10} -from_type stripe -to_type macro_port
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insert_pg_vias -nets {VDD VSS} -layers {metal4 metal5} -from_type stripe -to_type macro_port
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####################Check DRC####################
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check_drc -only false
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clean_drc -force
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check_drc -with_pre_route
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Executable
+124
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####################################################Read_RTL###########################################
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set search_path "${demo_chip_rtl_dir}/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone \
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${demo_chip_rtl_dir}/rtl/usb_phy/trunk/rtl/verilog \
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${demo_chip_rtl_dir}/rtl/usb/trunk/rtl/verilog \
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${demo_chip_rtl_dir}/rtl/nova/tags/Start/src \
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${demo_chip_rtl_dir}/rtl/nova/trunk/src \
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${demo_chip_rtl_dir}/rtl/demo_chip \
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${demo_chip_rtl_dir}/rtl/hpdmc/trunk/hpdmc_ddr32/rtl \
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${demo_chip_rtl_dir}/rtl/mem_wrapper \
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${demo_chip_rtl_dir}/rtl/lib_cells \
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${demo_chip_rtl_dir}/rtl/sondrel \
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${demo_chip_rtl_dir}/rtl/openmsp430 \
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${demo_chip_rtl_dir}/rtl/openmsp430/periph \
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${demo_chip_rtl_dir}/rtl/hpdmc/trunk/hpdmc_ddr32/rtl \
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${demo_chip_rtl_dir}/rtl/hpdmc/trunk/hpdmc_ddr32/rtl"
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set rtl_list { cpu_sys.v
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usb_sys.v
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nova_defines.v
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BitStream_buffer.v
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BitStream_controller.v
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bitstream_gclk_gen.v
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BitStream_parser_FSM_gating.v
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bs_decoding.v
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cavlc_consumed_bits_decoding.v
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cavlc_decoder.v
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||||
CodedBlockPattern_decoding.v
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dependent_variable_decoding.v
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DF_mem_ctrl.v
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||||
DF_pipeline.v
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||||
DF_reg_ctrl.v
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||||
DF_top.v
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||||
end_of_blk_decoding.v
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exp_golomb_decoding.v
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||||
ext_RAM_ctrl.v
|
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heading_one_detector.v
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||||
hybrid_pipeline_ctrl.v
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||||
Inter_mv_decoding.v
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||||
Inter_pred_CPE.v
|
||||
Inter_pred_LPE.v
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||||
Inter_pred_pipeline.v
|
||||
Inter_pred_reg_ctrl.v
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Inter_pred_sliding_window.v
|
||||
Inter_pred_top.v
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||||
Intra4x4_PredMode_decoding.v
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||||
Intra_pred_PE.v
|
||||
Intra_pred_pipeline.v
|
||||
Intra_pred_reg_ctrl.v
|
||||
Intra_pred_top.v
|
||||
IQIT.v
|
||||
level_decoding.v
|
||||
nC_decoding.v
|
||||
nova.v
|
||||
NumCoeffTrailingOnes_decoding.v
|
||||
pc_decoding.v
|
||||
QP_decoding.v
|
||||
ram_async_1r_sync_1w.v
|
||||
ram_sync_1r_sync_1w.v
|
||||
rec_DF_RAM_ctrl.v
|
||||
rec_gclk_gen.v
|
||||
reconstruction.v
|
||||
run_decoding.v
|
||||
sum.v
|
||||
syntax_decoding.v
|
||||
total_zeros_decoding.v
|
||||
Add.v
|
||||
ALU.v
|
||||
Compare.v
|
||||
Control.v
|
||||
CPZero.v
|
||||
Divide.v
|
||||
EXMEM_Stage.v
|
||||
Hazard_Detection.v
|
||||
IDEX_Stage.v
|
||||
IFID_Stage.v
|
||||
MemControl.v
|
||||
MEMWB_Stage.v
|
||||
Mux2.v
|
||||
Mux4.v
|
||||
Processor.v
|
||||
RegisterFile.v
|
||||
Register.v
|
||||
TrapDetect.v
|
||||
usbf_crc16.v
|
||||
usbf_crc5.v
|
||||
usbf_defines.v
|
||||
usbf_ep_rf_dummy.v
|
||||
usbf_ep_rf.v
|
||||
usbf_idma.v
|
||||
usbf_mem_arb.v
|
||||
usbf_pa.v
|
||||
usbf_pd.v
|
||||
usbf_pe.v
|
||||
usbf_pl.v
|
||||
usbf_rf.v
|
||||
usbf_utmi_if.v
|
||||
usbf_utmi_ls.v
|
||||
usbf_wb.v
|
||||
usbf_top.v
|
||||
usb_phy.v
|
||||
usb_rx_phy.v
|
||||
usb_tx_phy.v
|
||||
hpdmc_banktimer.v
|
||||
hpdmc_busif.v
|
||||
hpdmc_ctlif.v
|
||||
hpdmc_datactl.v
|
||||
hpdmc_mgmt.v
|
||||
hpdmc.v
|
||||
spartan6/hpdmc_ddrio.v
|
||||
spartan6/hpdmc_iddr32.v
|
||||
spartan6/hpdmc_iobuf32.v
|
||||
spartan6/hpdmc_obuft4.v
|
||||
spartan6/hpdmc_oddr32.v
|
||||
spartan6/hpdmc_oddr4.v
|
||||
nova_wrapper.v
|
||||
demo_chip.v
|
||||
powerdown_control.v
|
||||
IOBUF.v
|
||||
MemGen_32_12.v
|
||||
MemGen_32_14.v
|
||||
ddr_alignment.v
|
||||
ddr_pad_lib.v
|
||||
demo_chip.v }
|
||||
Executable
+38
@@ -0,0 +1,38 @@
|
||||
#########################################################
|
||||
# dse_base.tcl
|
||||
#
|
||||
# Description: Sets up the design for exploration
|
||||
#
|
||||
# Usage: source in Oasys-RTL Command prompt
|
||||
#
|
||||
# Dependencies: init_design.tcl
|
||||
#########################################################
|
||||
|
||||
#Initialize script parameters
|
||||
source scripts/init_design.tcl
|
||||
|
||||
#Disable warning messages
|
||||
message -enable false TA-116
|
||||
message -enable false LIB-136
|
||||
message -enable false LIB-114
|
||||
message -enable false NL-138
|
||||
message -enable false NL-120
|
||||
|
||||
source scripts/open_database.tcl
|
||||
###########################
|
||||
# If available, synthesize opencore files
|
||||
# instead of the pre-optimized ODB file
|
||||
############################
|
||||
# read_verilog $rtl_list -include $search_path
|
||||
# synthesize -module ${top_module} -map_to_scan -gate_clock
|
||||
# create_clock -period 2.50ns -name sysclk sysclk
|
||||
# read_sdc -verbose $demo_chip_sdc_files
|
||||
|
||||
#insert clk explorer here
|
||||
|
||||
#Optimize
|
||||
optimize -virtual
|
||||
report_clocks
|
||||
report_power
|
||||
report_design_metrics
|
||||
|
||||
Executable
+45
@@ -0,0 +1,45 @@
|
||||
#########################################################
|
||||
# dse_base.tcl
|
||||
#
|
||||
# Description: Sets up the design for exploration
|
||||
#
|
||||
# Usage: source in Oasys-RTL Command prompt
|
||||
#
|
||||
# Dependencies: init_design.tcl
|
||||
#########################################################
|
||||
|
||||
#Initialize script parameters
|
||||
set_explore -variable clock_period \
|
||||
-options { 2.00ns 2.25ns 2.50ns 2.75ns }
|
||||
|
||||
source scripts/init_design.tcl
|
||||
|
||||
#Disable warning messages
|
||||
message -enable false TA-116
|
||||
message -enable false LIB-136
|
||||
message -enable false LIB-114
|
||||
message -enable false NL-138
|
||||
message -enable false NL-120
|
||||
|
||||
source scripts/open_database.tcl
|
||||
###########################
|
||||
# If available, synthesize opencore files
|
||||
# instead of the pre-optimized ODB file
|
||||
############################
|
||||
# read_verilog $rtl_list -include $search_path
|
||||
# synthesize -module ${top_module} -map_to_scan -gate_clock
|
||||
# create_clock -period 2.50ns -name sysclk sysclk
|
||||
# read_sdc -verbose $demo_chip_sdc_files
|
||||
|
||||
explore clock_period {
|
||||
2.00ns { scale_clock -all -20 }
|
||||
2.25ns { scale_clock -all -10 }
|
||||
2.75ns { scale_clock -all 10 }
|
||||
}
|
||||
|
||||
#Optimize
|
||||
optimize -virtual
|
||||
report_clocks
|
||||
report_power
|
||||
report_design_metrics
|
||||
|
||||
Executable
+44
@@ -0,0 +1,44 @@
|
||||
set script_dir [file dirname [info script]]
|
||||
set ekit_dir [file normalize [file dirname ${script_dir}]]
|
||||
set libs_dir ${ekit_dir}/nangate/libs
|
||||
set lefs_dir ${ekit_dir}/nangate/lefs
|
||||
puts "Base Dir: ${ekit_dir}"
|
||||
|
||||
|
||||
#set lib(io) "${libs_dir}/lib_WCLCOM_ss_0p95v/LowPowerOpenCellLibrary_worst_low_ccs.lib \
|
||||
# ${libs_dir}/lib_WCLCOM_ss_0p95v/NangateOpenCellLibrary_worst_low_ccs.lib
|
||||
set lib(io) "${libs_dir}/IO.lib \
|
||||
${libs_dir}/PLL.lib \
|
||||
${libs_dir}/MemGen_16_10.lib"
|
||||
|
||||
set lib(hvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.lib \
|
||||
${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.lib"
|
||||
|
||||
set lib(svt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.lib \
|
||||
${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.lib"
|
||||
|
||||
set lib(lvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.lib \
|
||||
${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.lib"
|
||||
|
||||
#Specify the Physical libraries
|
||||
set lef(io) "${lefs_dir}/IO.lef \
|
||||
${lefs_dir}/PLL.lef \
|
||||
${lefs_dir}/MemGen_16_10.lef "
|
||||
# ${lefs_dir}/NangateOpenCellLibrary.macro.lef"
|
||||
set lef(hvt) ${lefs_dir}/NangateOpenCellLibrary_HVT.macro.lef
|
||||
set lef(svt) ${lefs_dir}/NangateOpenCellLibrary_SVT.macro.lef
|
||||
set lef(lvt) ${lefs_dir}/NangateOpenCellLibrary_LVT.macro.lef
|
||||
|
||||
#################################################
|
||||
### Build the library ODB
|
||||
#################################################
|
||||
read_lef ${lefs_dir}/tech_lef/NangateOpenCellLibrary.tech.lef
|
||||
read_ptf -temperature 0 ${ekit_dir}/nangate/ptf/NCSU_FreePDK_45nm.ptf
|
||||
foreach vt [list io hvt svt lvt] {
|
||||
puts "processing ${vt}... "
|
||||
read_library $lib(${vt})
|
||||
read_lef $lef(${vt})
|
||||
}
|
||||
write_db -data library ${ekit_dir}/libs/nangate_mvt.odb
|
||||
puts "wrote ${vt}: ${libs_dir}/libs/nangate_mvt.odb"
|
||||
|
||||
Executable
+31
@@ -0,0 +1,31 @@
|
||||
# Enable capture of commands
|
||||
config_shell -echo true
|
||||
|
||||
###################Top Module Specification###########
|
||||
set top_module "demo_chip"
|
||||
set max_route_layer "10"
|
||||
|
||||
# Set design file path variables
|
||||
set script_dir [file dirname [info script]]
|
||||
set ekit_dir [file dirname ${script_dir}]
|
||||
set demo_chip_rtl_dir "${ekit_dir}/demo_chip_rtl"
|
||||
set demo_chip_sdc_files "${ekit_dir}/constraints/demo_chip_func.sdc"
|
||||
set output_dir "${ekit_dir}/output"
|
||||
|
||||
|
||||
#set a consistant reporting format for timing
|
||||
config_report timing -format "cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain"
|
||||
|
||||
# Set DFT flow settings
|
||||
# To run the tessent DFT flow, please set the dft_flow variable to "tessent" from "oasys" and update tessent_build path
|
||||
set dft_flow tessent
|
||||
set tessent_build "/applications/SiemensEDA/siemenseda2023/tessent/bin/tessent"
|
||||
#set tessent_build $env(TESSENT)/bin/tessent
|
||||
|
||||
#Source the script that sets the path variables for all input files
|
||||
source ${script_dir}/demo_chip_design_files.tcl
|
||||
|
||||
echo "\n-----------------------------"
|
||||
echo "\nDone setting design variables"
|
||||
echo "\n-----------------------------\n"
|
||||
|
||||
Executable
+72
@@ -0,0 +1,72 @@
|
||||
#=======================================================#
|
||||
#Enable shift registers identification
|
||||
#=======================================================#
|
||||
infer_shift_registers
|
||||
|
||||
#=======================================================#
|
||||
#Define dft settings
|
||||
#=======================================================#
|
||||
define_test_pin -pin SCAN_ENABLE -scan 1 -default_scan_enable -create_port
|
||||
define_test_pin -pin scan_mode -scan 1
|
||||
define_test_clock -pin sysclk_byp -test_domain A
|
||||
connect_clock_gating_test_pin -test_pin SCAN_ENABLE
|
||||
|
||||
#Check the DFT violation and use autofix feature to adress them
|
||||
check_dft -auto_test_clock -auto_test_pins
|
||||
report_dft_violations
|
||||
|
||||
#=======================================================#
|
||||
# Pre fix_dft_violation database
|
||||
#=======================================================#
|
||||
write_db ${output_dir}/odb/demo_chip.oasysdft_pre_fix.odb
|
||||
|
||||
fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode
|
||||
check_dft
|
||||
report_dft_violations
|
||||
|
||||
#=======================================================#
|
||||
#Disable scan on enable_nova0_reg & enable_nova1_reg
|
||||
#=======================================================#
|
||||
set_dont_scan -verbose [get_cell enable_nova0_reg] true
|
||||
set_dont_scan -verbose [get_cell enable_nova1_reg] true
|
||||
|
||||
#=======================================================#
|
||||
#Final optimize
|
||||
#=======================================================#
|
||||
optimize
|
||||
write_db ${output_dir}/odb/demo_chip.oasysdft_post_fix.odb
|
||||
write_verilog ${output_dir}/demo_chip.oasysdft_post_fix.v
|
||||
report_timing
|
||||
report_endpoints
|
||||
report_power
|
||||
report_path_groups
|
||||
|
||||
|
||||
### Using partitioned based DFT Flow
|
||||
|
||||
# Should report 'default' as current dft partition
|
||||
current_dft_partition
|
||||
|
||||
# Define DFT partitions
|
||||
define_dft_partition P1 -instances {i_cpu_sys nova1}
|
||||
define_dft_partition P2 -instances { nova0}
|
||||
|
||||
|
||||
report_dft_partitions
|
||||
|
||||
## define_scan_chain
|
||||
define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port -partition P1
|
||||
|
||||
current_dft_partition P2
|
||||
# following definition scope is limited to P2
|
||||
define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port
|
||||
|
||||
# Resetting the partition definition to 'Default'
|
||||
reset_dft_partition
|
||||
|
||||
# Following scan chains should be created corresponding to 'Default' partition, meaning any logic outside of already coverd partitions.
|
||||
define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port
|
||||
|
||||
#connect_scan_chains
|
||||
connect_scan_chains -physical -mix_clock_edges
|
||||
|
||||
Executable
+107
@@ -0,0 +1,107 @@
|
||||
if {[info exists tessent_build] && [string match $dft_flow tessent]} {
|
||||
puts "INFO::using $tessent_build build to run the Tessent DFT flow"
|
||||
} else {
|
||||
puts "ERROR::To run the tessent DFT flow, Please set the following variables (as shown in the scripts/init_design.tcl file)"
|
||||
puts " - 'tessent_build' variable to the tessent executable"
|
||||
puts " # set dft_flow tessent"
|
||||
puts ""
|
||||
puts " - 'dft_flow' variable to 'tessent'"
|
||||
puts " # set tessent_build \$env(TESSENT)/bin/tessent"
|
||||
return 0
|
||||
}
|
||||
|
||||
#=======================================================#
|
||||
#Define dft settings
|
||||
#=======================================================#
|
||||
define_test_pin -pin scan_mode_pad/C -scan 1 -default_scan_enable
|
||||
define_test_pin -pin scan_mode -scan 1
|
||||
define_test_pin -pin reset_n_pad/C -scan 1
|
||||
define_test_pin -pin nova0/reset_n_sync_reg/Q -scan 1
|
||||
define_test_pin -pin nova1/reset_n_sync_reg/Q -scan 1
|
||||
define_test_clock -pin nova1/clk
|
||||
define_test_clock -pin nova0/clk
|
||||
define_test_clock -pin usbclk_byp
|
||||
define_test_clock -pin sysclk_byp
|
||||
|
||||
connect_clock_gating_test_pin -test_pin scan_mode_pad/C
|
||||
|
||||
#Check the DFT violation and use autofix feature to adress them
|
||||
check_dft -auto_test_clock -auto_test_pins
|
||||
|
||||
#=======================================================#
|
||||
# Pre fix_dft_violation database
|
||||
#=======================================================#
|
||||
write_db ${output_dir}/odb/demo_chip.tessent_pre_fix.odb
|
||||
|
||||
fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode_pad/C
|
||||
check_dft
|
||||
report_dft_violations
|
||||
|
||||
#=======================================================#
|
||||
#Final optimize
|
||||
#=======================================================#
|
||||
optimize
|
||||
write_db ${output_dir}/odb/demo_chip.tessent_post_fix.odb
|
||||
write_verilog ${output_dir}/demo_chip.tessent_post_fix.v
|
||||
report_timing
|
||||
report_endpoints
|
||||
report_power
|
||||
report_path_groups
|
||||
|
||||
#========================================================#
|
||||
# Formalpro verification command
|
||||
#========================================================#
|
||||
|
||||
#verify ${output_dir}/verilog/post_optimize.v -base_directory post_optimize
|
||||
|
||||
|
||||
#=======================================================#
|
||||
# configuring Tessent build
|
||||
#=======================================================#
|
||||
#Specify the path to Tessent exec.
|
||||
|
||||
config_tessent -exec_path $tessent_build
|
||||
|
||||
#=======================================================#
|
||||
# Tessent TPI
|
||||
#=======================================================#
|
||||
|
||||
set fastscan_path "${ekit_dir}/libs/fastscan"
|
||||
config_tessent -ignore_clock_gating "on"
|
||||
set lib_list [glob -nocomplain $fastscan_path/*.fslib ]
|
||||
config_tessent -library $lib_list
|
||||
config_tessent_tpi -total_number 2% -control_point_enable control_test_point_en -observe_point_enable observe_test_point_en
|
||||
|
||||
run_tessent_tpi
|
||||
|
||||
#========================================================#
|
||||
# Formalpro verification command
|
||||
#========================================================#
|
||||
|
||||
#verify ${output_dir}/verilog/post_tpi.v -base_directory post_tpi
|
||||
|
||||
|
||||
#=======================================================#
|
||||
# Tessent SCAN
|
||||
#=======================================================#
|
||||
check_dft
|
||||
for {set i 1} {$i < 5} {incr i} {
|
||||
define_scan_chain -scan_in SI_$i -scan_out SO_$i -create_port
|
||||
}
|
||||
|
||||
run_tessent_scan
|
||||
|
||||
write_db ${output_dir}/odb/demo_chip.tessent_post_scan.odb
|
||||
write_verilog ${output_dir}/demo_chip.tessent_post_scan.v
|
||||
report_power
|
||||
report_path_groups
|
||||
report_scan_chains
|
||||
|
||||
#========================================================#
|
||||
#Formalpro verification command
|
||||
#========================================================#
|
||||
|
||||
#verify ${output_dir}/verilog/post_dft.v -base_directory post_dft
|
||||
|
||||
|
||||
|
||||
Executable
+43
@@ -0,0 +1,43 @@
|
||||
#########################################################
|
||||
# open_database.tcl
|
||||
#
|
||||
# Description: Load the generated Oasys-RTL databases (.odb)
|
||||
# into the tool
|
||||
#
|
||||
# Usage: source in Oasys-RTL Command prompt
|
||||
#
|
||||
# Dependencies: 1_init_design.tcl
|
||||
# Existing odb created from the
|
||||
# Launched from Oasys-RTL shell
|
||||
#
|
||||
#########################################################
|
||||
|
||||
# Check if dependent scripts have been loaded
|
||||
if {![info exists top_module]} {
|
||||
source scripts/init_design.tcl
|
||||
}
|
||||
|
||||
if { ![info exists ekit_dir] } { return }
|
||||
|
||||
# Read existing Oasys-RTL database (design and libraries)
|
||||
if {[file exists ${ekit_dir}/output/odb/demo_chip.oasys_final.odb]} {
|
||||
puts "Using ODB from output directory"
|
||||
read_db ${ekit_dir}/output/odb/demo_chip.oasys_final.odb
|
||||
} elseif {[file exists ${ekit_dir}/demo_chip_rtl/demo_chip.odb]} {
|
||||
puts "Using pre-defined ODB from demo_chip_rtl directory"
|
||||
read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb
|
||||
} else {
|
||||
puts "unable to locate ODB file for demo_chip design"
|
||||
}
|
||||
|
||||
# Report DFT if scan chains exist
|
||||
if { [get_scan_chains] > 0 } {
|
||||
check_dft
|
||||
report_scan_chains
|
||||
}
|
||||
|
||||
# Report design
|
||||
puts "Running timing reports..."
|
||||
report_path_groups
|
||||
report_timing
|
||||
|
||||
Executable
+8
@@ -0,0 +1,8 @@
|
||||
set rtVersion [get_parameter version]
|
||||
|
||||
## remove all placement
|
||||
delete_physical -all -verbose true
|
||||
## create a new rectilinear die given a list of points
|
||||
create_chip -points {{0 0} {0 700} {700 700} {700 1600} {2500 1600} {2500 0} } -overwrite true -verbose true
|
||||
report_design_metrics
|
||||
#optimize -place
|
||||
Reference in New Issue
Block a user