Initial commit

2026-05-29 10:19:13 +02:00
commit fedfd92270
726 changed files with 542654 additions and 0 deletions
@@ -0,0 +1,87 @@
+#########################################################
+#                 4_mbist_tessent_shell.tcl
+#
+# Description:  MemoryBIST insertion für RISC-V Design
+#
+# Usage:        Im Tessent Shell Prompt:
+#               SETUP> set script_dir "scripts_risc_v"
+#               SETUP> set ekit_dir "."
+#               SETUP> source scripts_risc_v/4_mbist_tessent_shell.tcl
+#
+# Dependencies: - nangate_complete.tcelllib (aus gen_tcelllib.tcl)
+#               - riscv.tessent_post_scan.v (aus Oasys DFT Flow)
+#               - MemGen_16_10.memlib
+#########################################################
+set script_dir "scripts_risc_v"
+
+
+if {![info exists ekit_dir]} {
+    set ekit_dir [file dirname ${script_dir}]
+}
+
+#----------------------------------------------------------
+# 1. Kontext setzen - Gate-Level Netlist
+#----------------------------------------------------------
+set_context dft -no_rtl
+
+#----------------------------------------------------------
+# 2. Libraries laden
+#----------------------------------------------------------
+# Tessent Cell Library
+read_cell_library ${ekit_dir}/output/nangate_complete.tcelllib
+
+# Memory BIST Model für MemGen_16_10
+read_core_descriptions ${ekit_dir}/libs/MemGen_16_10.memlib
+
+#----------------------------------------------------------
+# 3. Gate-Level Netlist laden
+#----------------------------------------------------------
+read_verilog ${ekit_dir}/output/riscv.tessent_post_scan.v
+
+#----------------------------------------------------------
+# 4. Top-Level und Design-Level setzen
+#----------------------------------------------------------
+set_current_design cpu
+set_design_level chip
+
+#----------------------------------------------------------
+# 5. MBIST Anforderungen setzen
+#----------------------------------------------------------
+set_dft_specification_requirements -memory_test on
+
+# Gefundene Memory-Instanzen anzeigen
+report_memory_instances
+
+#----------------------------------------------------------
+# 6. Clocks definieren
+#----------------------------------------------------------
+add_clocks clk_25mhz -period 40ns -label mbist_clk
+
+#----------------------------------------------------------
+# 7. Design Rule Check
+#----------------------------------------------------------
+check_design_rules
+
+#----------------------------------------------------------
+# 8. DFT Specification erstellen und verarbeiten
+#----------------------------------------------------------
+set dft_spec [create_dft_specification]
+report_config_data $dft_spec
+validate_dft_specification
+process_dft_specification
+extract_icl
+
+#----------------------------------------------------------
+# 9. Pattern Generation
+#----------------------------------------------------------
+set pat_spec [create_patterns_specification]
+process_patterns_specification
+
+#----------------------------------------------------------
+# 10. Simulation und Synthese
+#----------------------------------------------------------
+run_testbench_simulations
+check_testbench_simulations
+run_synthesis
+
+exit