# OpenFile ./cpu_tb.sv
ls
# alu_tb.sv  decoder_tb.sv   pc_tb.sv        transcript    
# cpu_tb.sv  main_mem_tb.sv  reg_file_tb.sv  work          
vsim compile.tcl
# vsim compile.tcl 
# Start time: 11:01:25 on Nov 28,2025
# ** Error (suppressible): (vsim-19) Failed to access library 'compile' at "compile".
# No such file or directory. (errno = ENOENT)
# Error loading design
# End time: 11:01:25 on Nov 28,2025, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
ls
# alu_tb.sv  decoder_tb.sv   pc_tb.sv        transcript    
# cpu_tb.sv  main_mem_tb.sv  reg_file_tb.sv  work          
cd ..
ls
# rtl  verilator  wave_configs        
cd ..
pwd
# C:/PhD/RISC-V Design Course Material/RISC-V Desgin Course - Complete Source Code/riscv_in3days-public/hw
cd ..
ls
# README.md  doc  hw  sw          
cd ..
ls
# riscv_in3days-public        
cd ..
ls
# Course Introduction & Closing - Public.pdf   
# Day 1                                        
# Day 2                                        
# Day 3                                        
# Day 4                                        
# RISC-V Desgin Course - Complete Source Code  
# References                                   
cd ..
cd ..
la
# ambiguous command name "la": label labelframe langOf lappend lassign lattice_edition layout
ls
# Drivers        Program Files (x86)    inetpub         
# DumpStack.log  Steam_Community_Markt  intelFPGA       
# Lukas          Users                  intelFPGA_lite  
# PhD            Windows                vfcompat.dll    
# ProcLogs       appverifUI.dll                         
# Program Files  flexlm                                 
pwd
# C:/
ls
# Drivers        Program Files (x86)    inetpub         
# DumpStack.log  Steam_Community_Markt  intelFPGA       
# Lukas          Users                  intelFPGA_lite  
# PhD            Windows                vfcompat.dll    
# ProcLogs       appverifUI.dll                         
# Program Files  flexlm                                 
cd PhD
ls
# Code                           compile.tcl  
# RISC-V Design Course Material               
cd RISC-V Design Course Material
# wrong # args: should be "cd ?dirName?"
ls
# Code                           compile.tcl  
# RISC-V Design Course Material               
ls
# Code                           compile.tcl  
# RISC-V Design Course Material               
cd RISC-V Design Course Material
# wrong # args: should be "cd ?dirName?"
ls
# Code                           compile.tcl  
# RISC-V Design Course Material               
run compile.tcl
# No Design Loaded!
compile.tcl
# couldn't execute ".\compile.tcl": no such file or directory
run compile.tcl
# No Design Loaded!