//  *********************************************************************************************
//  Project Version  : v1.0
//  Project          : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
//  -----
//  Copyright (c)    : 2025 Fraunhofer IIS, Department IDS
//  Created          : 12.Jun.2025  by Lund University [commit 5b1e415]
//  Last Modified    : 23.Oct.2025  by Bomin Kim       [commit 2f8f03d]
//  -----
//  HISTORY          : Date         By         Comments
//                     -----------  ---------  -------------------------------------------------
//                     15.Oct.2025  Bomin Kim  Moved NextPC logic from decoder into PC
//                     15.Oct.2025  Bomin Kim  Removed reset condition from combinational logic
//  *********************************************************************************************


module pc (
  output logic[31:0] CurrentPC,
  input  logic[31:0] JumpOrBranchPC,
  input  logic       JumpOrBranch,
  output logic[31:0] NextPC,
  input  logic       reset,
  input  logic       clk
);

  // NextPC logic; next-state function
  always_comb begin : Next_PC
    if (JumpOrBranch) NextPC = JumpOrBranchPC;
    else NextPC = CurrentPC + 4;
  end

  // CurrentPC logic; state register
  always_ff @(posedge clk) begin
    if (reset) CurrentPC <= '0;
    else       CurrentPC <= NextPC;
  end

endmodule