m255 K4 z2 Z0 !s99 nomlopt !s11f vlog 2023.2 2023.04, Apr 11 2023 13 !s112 1.1 !i10d 8192 !i10e 25 !i10f 100 cModel Technology Z1 d/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl valu Z2 2hw/rtl/pc.sv|hw/rtl/reg_file.sv|hw/rtl/alu.sv|hw/rtl/MemGen_32_11.sv|hw/rtl/main_mem.sv|hw/rtl/decoder.sv|hw/rtl/cpu.sv Z3 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92 Z4 !s110 1777461358 !i10b 1 !s100 c7@e^4VRKhKUEEThRE>IL3 IRF@[`@^VS_z[3JdlC^jk?0 S1 R1 w1776171120 8hw/rtl/alu.sv Fhw/rtl/alu.sv !i122 1 L0 16 37 Z5 VDg1SIo80bB@j0V0VzS_@n1 Z6 OL;L;2023.2;77 r1 !s85 0 31 Z7 !s108 1777461358.000000 Z8 !s107 hw/rtl/cpu.sv|hw/rtl/decoder.sv|hw/rtl/main_mem.sv|hw/rtl/MemGen_32_11.sv|hw/rtl/alu.sv|hw/rtl/reg_file.sv|hw/rtl/pc.sv| Z9 !s90 -sv|-lint|-pedanticerrors|-f|rtl_flist.f| !i113 0 Z10 o-sv -lint -pedanticerrors -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact Z11 tCvgOpt 0 vcpu R2 R3 R4 !i10b 1 !s100 W5YnilUcQ_V2@UXTF:=cJ3 I8K0UGGAJE3 IlkV3GA3k