set_context patterns -scan

set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir

read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib
read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib

read_design cpu -design_id Scan_0

add_black_boxes -modules { MemGen_16_10 }
add_black_boxes -modules { MemGen_32_11 }
add_black_boxes -modules { main_mem }

set_current_design cpu
set_design_level physical_block

# import_scan_mode reads the TCD which now includes clk12p5_reg/Q as TestClock
import_scan_mode unwrapped

set_system_mode analysis

report_clocks
report_drc_rules

set_fault_type stuck
add_faults -all
create_patterns

report_statistics
report_faults -summary

write_patterns cpu_patterns.stil         -stil    -replace
write_patterns cpu_patterns_serial.v     -verilog -serial   -replace
write_tsdb_data -replace

exit