857 lines
27 KiB
Verilog
Executable File
857 lines
27 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////
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// Design : demo_chip
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// Author(s) :
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// Creation date : August 9,2013
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// Copyright (C) ...
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////////////////////////////////////////////////////////////////////
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// Description: demo_chip instantiates the following modules:
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// 1 MIPS 32r1 CPU
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// 2 nova decoder wrapper
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// 3 4 * HPDMC DDR controllers
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// 4 USB controller + PHY
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//
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////////////////////////////////////////////////////////////////////
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module demo_chip(
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output mclk, // Main system clock (used by external memories)
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input reset_n,
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//
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// First H264 Decoder Pins
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//
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input [15:0] BS_data_0,
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output BS_ren_0,
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output [16:0] BS_addr_0,
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//
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// Second H264 Decoder Pins
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//
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input [15:0] BS_data_1,
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output BS_ren_1,
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output [16:0] BS_addr_1,
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//
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// Microcontroller pins
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//
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input lfxt_clk, // Low frequency reference (typ 10MHz)
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input nmi, // Non-maskable interrupt (asynchronous and non-glitchy)
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// DDR0
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output ddr0_cke,
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output ddr0_cs_n,
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output ddr0_we_n,
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output ddr0_cas_n,
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output ddr0_ras_n,
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output [12:0] ddr0_adr,
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output [1:0] ddr0_ba,
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output [3:0] ddr0_dm,
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inout [31:0] ddr0_dq,
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inout [3:0] ddr0_dqs,
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// DDR1
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output ddr1_cke,
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output ddr1_cs_n,
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output ddr1_we_n,
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output ddr1_cas_n,
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output ddr1_ras_n,
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output [12:0] ddr1_adr,
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output [1:0] ddr1_ba,
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output [3:0] ddr1_dm,
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inout [31:0] ddr1_dq,
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inout [3:0] ddr1_dqs,
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// DDR2
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output ddr2_cke,
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output ddr2_cs_n,
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output ddr2_we_n,
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output ddr2_cas_n,
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output ddr2_ras_n,
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output [12:0] ddr2_adr,
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output [1:0] ddr2_ba,
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output [3:0] ddr2_dm,
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inout [31:0] ddr2_dq,
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inout [3:0] ddr2_dqs,
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// DDR3
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_we_n,
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output ddr3_cas_n,
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output ddr3_ras_n,
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output [12:0] ddr3_adr,
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output [1:0] ddr3_ba,
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output [3:0] ddr3_dm,
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inout [31:0] ddr3_dq,
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inout [3:0] ddr3_dqs,
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// USB
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inout usb_plus, usb_minus,
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//
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input scan_mode,
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input sysclk_byp,
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input usbclk_byp
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);
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// Internal chip side pad connections
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wire lfxt_clk_i; // Main system clock (used by external memories)
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wire reset_n_i;
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wire nmi_i; // Non-maskable interrupt (asynchronous and non-glitchy)
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wire mclk_i; // Main system clock (used by external memories)
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wire scan_mode_i;
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wire sysclk_byp_i;
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wire usbclk_byp_i;
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// DDR
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wire ddr0_cke_i, ddr0_cs_n_i, ddr0_we_n_i, ddr0_cas_n_i, ddr0_ras_n_i,
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ddr1_cke_i, ddr1_cs_n_i, ddr1_we_n_i, ddr1_cas_n_i, ddr1_ras_n_i,
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ddr2_cke_i, ddr2_cs_n_i, ddr2_we_n_i, ddr2_cas_n_i, ddr2_ras_n_i,
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ddr3_cke_i, ddr3_cs_n_i, ddr3_we_n_i, ddr3_cas_n_i, ddr3_ras_n_i;
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wire [12:0] ddr0_adr_i, ddr1_adr_i, ddr2_adr_i, ddr3_adr_i;
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wire [1:0] ddr0_ba_i, ddr1_ba_i, ddr2_ba_i, ddr3_ba_i;
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wire [3:0] ddr0_dm_i, ddr1_dm_i, ddr2_dm_i, ddr3_dm_i;
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wire [15:0] BitStream_buffer_input_0_i;
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wire BitStream_ram_ren_0_i;
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wire [16:0] BitStream_ram_addr_0_i;
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wire [15:0] BitStream_buffer_input_1_i;
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wire BitStream_ram_ren_1_i;
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wire [16:0] BitStream_ram_addr_1_i;
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// wire [15:0] BS_data_0; //added by sudhish for missing declarations on pads
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// wire [15:0] BS_data_1;
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wire [31:0] dmem_din; // Data Memory data input
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wire [29:0] dmem_addr; // Data Memory address
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wire [3:0] dmem_wen; // Data Memory write enable (low active)
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wire dmem_cen; // Data Memory write enable (low active)
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wire [31:0] power_control; // Power switch powerdwon control
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wire [31:0] power_iso; // Power switch isolation control
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wire [31:0] power_ack; // Power switch acknowledge
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wire power_control_0;
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wire power_ack_0;
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// QSG wire power_ack_2;
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// QSG wire power_control_2;
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wire smclk;
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wire pll_clk, pll_clk_o;
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wire aclk;
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wire dco_clk;
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reg enable_nova0, enable_nova1;
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wire mclk_nova0, mclk_nova1;
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wire ext_frame_RAM0_cs_n;
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wire ext_frame_RAM0_wr;
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wire [13:0] ext_frame_RAM0_addr;
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wire [31:0] ext_frame_RAM0_data;
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wire [63:0] fml_do_ddr0;
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wire ext_frame_RAM1_cs_n;
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wire ext_frame_RAM1_wr;
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wire [13:0] ext_frame_RAM1_addr;
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wire [31:0] ext_frame_RAM1_data;
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wire [63:0] fml_do_ddr1;
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wire [31:0] dis_frame_RAM_din_0;
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wire ext_frame_RAM2_cs_n;
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wire ext_frame_RAM2_wr;
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wire [13:0] ext_frame_RAM2_addr;
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wire [31:0] ext_frame_RAM2_data;
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wire [63:0] fml_do_ddr2;
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wire ext_frame_RAM3_cs_n;
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wire ext_frame_RAM3_wr;
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wire [13:0] ext_frame_RAM3_addr;
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wire [31:0] ext_frame_RAM3_data;
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wire [63:0] fml_do_ddr3;
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wire [31:0] dis_frame_RAM_din_1;
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// USB
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wire usb_clk, usb_clk_o;
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wire usb_txdp, usb_txdn, usb_txoe;
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wire usb_rxd, usb_rxdp, usb_rxdn;
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wire [7:0] usb_DataOut;
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wire usb_TxValid;
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wire usb_TxReady;
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wire [7:0] usb_DataIn;
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wire usb_RxValid;
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wire usb_RxActive;
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wire usb_RxError;
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wire [1:0] usb_LineState;
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wire usb_inta, usb_intb;
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wire [4:0] Interrupts; // 5 general-purpose hardware interrupts
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// Define clocks - all from PLL
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assign smclk = pll_clk;
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assign mclk_i = pll_clk;
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assign mclk_n = !pll_clk;
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assign dqs_clk = pll_clk;
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assign dqs_clk_n = !pll_clk;
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assign aclk = pll_clk;
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assign mclk_i = pll_clk;
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assign dco_clk = pll_clk;
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// ---------------------------------
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// External pads (non-DDR)
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// ---------------------------------
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PADBID lfxt_clk_pad ( .I(1'b0), .OEN(1'b1), .PAD(lfxt_clk), .C(lfxt_clk_i) );
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PADBID reset_n_pad ( .I(1'b0), .OEN(1'b1), .PAD(reset_n), .C(reset_n_i) );
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PADBID nmi_pad ( .I(1'b0), .OEN(1'b1), .PAD(nmi), .C(nmi_i) );
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PADBID mclk_pad ( .I(mclk_i), .OEN(1'b0), .PAD(mclk), .C() );
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PADBID BS_ren_0_pad ( .I(BitStream_ram_ren_0_i), .OEN(1'b0), .PAD(BS_ren_0), .C() );
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PADBID BS_ren_1_pad ( .I(BitStream_ram_ren_1_i), .OEN(1'b0), .PAD(BS_ren_1), .C() );
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PADBID scan_mode_pad ( .I(1'b0), .OEN(1'b1), .PAD(scan_mode), .C(scan_mode_i) );
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// PADBID sysclk_byp_pad ( .I(1'b0), .OEN(1'b1), .PAD(sysclk_byp), .C(sysclk_byp_i) );
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//PADBID usbclk_byp_pad ( .I(1'b0), .OEN(1'b1), .PAD(usbclk_byp), .C(usbclk_byp_i) );
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PADCLK sysclk_byp_pad ( .PAD(sysclk_byp), .C(sysclk_byp_i) );
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PADCLK usbclk_byp_pad ( .PAD(usbclk_byp), .C(usbclk_byp_i) );
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genvar i, ddr;
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// Data buses
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generate
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for (i = 0; i <= 15; i = i + 1) begin
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PADBID BS_data_0_pad ( .I(1'b0), .OEN(1'b1), .PAD(BS_data_0[i]), .C(BitStream_buffer_input_0_i[i]) );
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PADBID BS_data_1_pad ( .I(1'b0), .OEN(1'b1), .PAD(BS_data_1[i]), .C(BitStream_buffer_input_1_i[i]) );
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end
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endgenerate
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// Address buses
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generate
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for (i = 0; i <= 16; i = i + 1) begin
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PADBID BS_addr_0_pad ( .I(BitStream_ram_addr_0_i[i]), .OEN(1'b0), .PAD(BS_addr_0[i]), .C() );
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PADBID BS_addr_1_pad ( .I(BitStream_ram_addr_1_i[i]), .OEN(1'b0), .PAD(BS_addr_1[i]), .C() );
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end
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endgenerate
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PADBID i_usb_pad_plus ( .I(usb_txdp), .OEN(usb_txoe), .PAD(usb_plus), .C(usb_rxdp) );
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PADBID i_usb_pad_minus ( .I(usb_txdn), .OEN(usb_txoe), .PAD(usb_minus), .C(usb_rxdn) );
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assign usb_rxd = usb_rxdp && usb_rxdn;
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// ---------------------------------
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// DDR output pads (data pads are in the PHY module
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// ---------------------------------
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PADBID ddr0_cke_pad ( .I(ddr0_cke_i), .OEN(1'b0), .PAD(ddr0_cke), .C() );
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PADBID ddr0_cs_n_pad ( .I(ddr0_cs_n_i), .OEN(1'b0), .PAD(ddr0_cs_n), .C() );
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PADBID ddr0_we_n_pad ( .I(ddr0_we_n_i), .OEN(1'b0), .PAD(ddr0_we_n), .C() );
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PADBID ddr0_cas_n_pad ( .I(ddr0_cas_n_i), .OEN(1'b0), .PAD(ddr0_cas_n), .C() );
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PADBID ddr0_ras_n_pad ( .I(ddr0_ras_n_i), .OEN(1'b0), .PAD(ddr0_ras_n), .C() );
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PADBID ddr1_cke_pad ( .I(ddr1_cke_i), .OEN(1'b0), .PAD(ddr1_cke), .C() );
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PADBID ddr1_cs_n_pad ( .I(ddr1_cs_n_i), .OEN(1'b0), .PAD(ddr1_cs_n), .C() );
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PADBID ddr1_we_n_pad ( .I(ddr1_we_n_i), .OEN(1'b0), .PAD(ddr1_we_n), .C() );
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PADBID ddr1_cas_n_pad ( .I(ddr1_cas_n_i), .OEN(1'b0), .PAD(ddr1_cas_n), .C() );
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PADBID ddr1_ras_n_pad ( .I(ddr1_ras_n_i), .OEN(1'b0), .PAD(ddr1_ras_n), .C() );
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PADBID ddr2_cke_pad ( .I(ddr2_cke_i), .OEN(1'b0), .PAD(ddr2_cke), .C() );
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PADBID ddr2_cs_n_pad ( .I(ddr2_cs_n_i), .OEN(1'b0), .PAD(ddr2_cs_n), .C() );
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PADBID ddr2_we_n_pad ( .I(ddr2_we_n_i), .OEN(1'b0), .PAD(ddr2_we_n), .C() );
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PADBID ddr2_cas_n_pad ( .I(ddr2_cas_n_i), .OEN(1'b0), .PAD(ddr2_cas_n), .C() );
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PADBID ddr2_ras_n_pad ( .I(ddr2_ras_n_i), .OEN(1'b0), .PAD(ddr2_ras_n), .C() );
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PADBID ddr3_cke_pad ( .I(ddr3_cke_i), .OEN(1'b0), .PAD(ddr3_cke), .C() );
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PADBID ddr3_cs_n_pad ( .I(ddr3_cs_n_i), .OEN(1'b0), .PAD(ddr3_cs_n), .C() );
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PADBID ddr3_we_n_pad ( .I(ddr3_we_n_i), .OEN(1'b0), .PAD(ddr3_we_n), .C() );
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PADBID ddr3_cas_n_pad ( .I(ddr3_cas_n_i), .OEN(1'b0), .PAD(ddr3_cas_n), .C() );
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PADBID ddr3_ras_n_pad ( .I(ddr3_ras_n_i), .OEN(1'b0), .PAD(ddr3_ras_n), .C() );
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generate
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for (i = 0; i <= 12; i = i + 1) begin
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PADBID ddr0_adr_pad ( .I(ddr0_adr_i[i]), .OEN(1'b0), .PAD(ddr0_adr[i]), .C() );
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PADBID ddr1_adr_pad ( .I(ddr1_adr_i[i]), .OEN(1'b0), .PAD(ddr1_adr[i]), .C() );
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PADBID ddr2_adr_pad ( .I(ddr2_adr_i[i]), .OEN(1'b0), .PAD(ddr2_adr[i]), .C() );
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PADBID ddr3_adr_pad ( .I(ddr3_adr_i[i]), .OEN(1'b0), .PAD(ddr3_adr[i]), .C() );
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end
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endgenerate
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generate
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for (i = 0; i <= 1; i = i + 1) begin
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PADBID ddr0_ba_pad ( .I(ddr0_ba_i[i]), .OEN(1'b0), .PAD(ddr0_ba[i]), .C() );
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PADBID ddr1_ba_pad ( .I(ddr1_ba_i[i]), .OEN(1'b0), .PAD(ddr1_ba[i]), .C() );
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PADBID ddr2_ba_pad ( .I(ddr2_ba_i[i]), .OEN(1'b0), .PAD(ddr2_ba[i]), .C() );
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PADBID ddr3_ba_pad ( .I(ddr3_ba_i[i]), .OEN(1'b0), .PAD(ddr3_ba[i]), .C() );
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end
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endgenerate
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generate
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for (i = 0; i <= 3; i = i + 1) begin
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PADBID ddr0_dm_pad ( .I(ddr0_dm_i[i]), .OEN(1'b0), .PAD(ddr0_dm[i]), .C() );
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PADBID ddr1_dm_pad ( .I(ddr1_dm_i[i]), .OEN(1'b0), .PAD(ddr1_dm[i]), .C() );
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PADBID ddr2_dm_pad ( .I(ddr2_dm_i[i]), .OEN(1'b0), .PAD(ddr2_dm[i]), .C() );
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PADBID ddr3_dm_pad ( .I(ddr3_dm_i[i]), .OEN(1'b0), .PAD(ddr3_dm[i]), .C() );
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end
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endgenerate
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// ---------------------------------
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// Peripheral Interface bus
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// ---------------------------------
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wire [15:0] per_dout; // Register data output to microcontroller
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wire [15:0] per_dout_nova0; // Register data output from nova0
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wire [15:0] per_dout_nova1; // Register data output from nova1
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wire [31:0] per_dout_ddr0; // Register data output from ddr0
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wire [31:0] per_dout_ddr1; // Register data output from ddr0
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wire [31:0] per_dout_ddr2; // Register data output from ddr0
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wire [31:0] per_dout_ddr3; // Register data output from ddr0
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wire [31:0] per_dout_usb; // Register data output from USB
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wire [31:0] per_dout_pctl; // Register data output from USB
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wire [13:0] per_addr; // Register address
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wire [31:0] per_din; // Register data input
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wire [1:0] per_we; // Register write enable (high active)
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wire per_en; // Register enable (high active)
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wire per_rd; // Register read
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assign per_din = dmem_din;
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assign per_dout = {15'h0000,per_dout_nova0} ||
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{15'h0000,per_dout_nova1[15:0]} ||
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per_dout_ddr0 ||
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per_dout_ddr1 ||
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per_dout_ddr2 ||
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per_dout_ddr3 ||
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per_dout_usb ||
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per_dout_pctl ||
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32'h00000000;
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assign per_en = dmem_addr[29];
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assign per_we[0] = dmem_addr[29] && dmem_wen[0];
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assign per_we[1] = dmem_addr[29] && dmem_wen[1];
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assign per_rd = per_en && !per_we[0];
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assign per_addr = dmem_addr[13:0];
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//assign DataMem_In = dmem_addr[29] ? per_dout : dmem_dout;
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wire NMI; // Non-maskable interrupt
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wire DataMem_Ready;
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wire DataMem_Read;
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wire [3:0] DataMem_Write; // 4-bit Write; one for each byte in word.
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wire [29:0] DataMem_Address; // Addresses are words; not bytes.
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wire [31:0] DataMem_Out;
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// Instruction Memory Interface
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wire [31:0] InstMem_In;
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wire [29:0] InstMem_Address; // Addresses are words; not bytes.
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wire InstMem_Ready;
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wire InstMem_Read;
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wire [7:0] IP; // Pending interrupts (diagnostic)
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assign Interrupts = { 3'b0, usb_inta, usb_intb } ;
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// ---------------------------------
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// MIPS CPU
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// ---------------------------------
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cpu_sys i_cpu_sys (
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.clock(smclk),
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.reset(reset_n_i),
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.Interrupts(Interrupts), // 5 general-purpose hardware interrupts
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.NMI(nmi_i), // Non-maskable interrupt
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// Data Memory Interface
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.per_dout(per_dout),
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.DataMem_Read(dmem_rd),
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.DataMem_Write(dmem_wen), // 4-bit Write, one for each byte in word.
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.DataMem_Address(dmem_addr), // Addresses are words, not bytes.
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.DataMem_Out(dmem_din)
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);
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// ---------------------------------
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// Powerdown register
|
|
// ---------------------------------
|
|
|
|
// Tie off pre-layout - will connect to power switches
|
|
// assign power_ack = 32'hffff_ffff;
|
|
|
|
powerdown_control powerdown_control (
|
|
.clk(mclk_i),
|
|
.reset_n(reset_n_i),
|
|
.per_addr(per_addr),
|
|
.per_din(per_din),
|
|
.per_en(per_en),
|
|
.per_we(per_we[0]),
|
|
.per_rd(per_rd),
|
|
.per_dout(per_dout_pctl),
|
|
.power_control(power_control),
|
|
.power_ack(power_ack),
|
|
.power_iso(power_iso)
|
|
);
|
|
|
|
//dummy_connector dummy_connector (.power_control(power_control), .power_iso(power_iso), .power_ack(power_ack) );
|
|
|
|
// NOVA 0 clock gate
|
|
always @(negedge mclk_i ) enable_nova0 <= power_iso[0];
|
|
AND2_X1_HVT i_nova0_cg (.A1(mclk_i), .A2(enable_nova0), .ZN(mclk_nova0) );
|
|
|
|
///////////////////
|
|
// NOVA decoders //
|
|
///////////////////
|
|
nova_wrapper nova0 (
|
|
.clk(mclk_nova0),
|
|
.clk_reg(smclk),
|
|
.reset_n(reset_n_i),
|
|
.per_dout(per_dout_nova0),
|
|
.per_addr(per_addr),
|
|
.per_din(per_din[15:0]),
|
|
.per_en(per_en),
|
|
.per_we(per_we),
|
|
.BitStream_buffer_input(BitStream_buffer_input_0_i),
|
|
.BitStream_ram_ren(BitStream_ram_ren_0_i),
|
|
.BitStream_ram_addr(BitStream_ram_addr_0_i),
|
|
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
|
|
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
|
|
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
|
|
.ext_frame_RAM0_data(ext_frame_RAM0_data),
|
|
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
|
|
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
|
|
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
|
|
.ext_frame_RAM1_data(ext_frame_RAM1_data),
|
|
.dis_frame_RAM_din(dis_frame_RAM_din_0),
|
|
.power_ack(power_ack_0),
|
|
.power_control(power_control_0)
|
|
);
|
|
|
|
// DDR port 0
|
|
|
|
// Dummy register to create control signal
|
|
reg [7:0] fml_sel_ddr0;
|
|
always @ (posedge mclk_nova0 )
|
|
begin
|
|
if ( ext_frame_RAM0_cs_n == 1'b0 )
|
|
if ( ext_frame_RAM0_wr )
|
|
fml_sel_ddr0 <= dis_frame_RAM_din_0[7:0];
|
|
else
|
|
fml_sel_ddr0 <= dis_frame_RAM_din_0[15:8];
|
|
end
|
|
// Create to get a 2 bit pll_stat for DDR
|
|
wire sys_pll_lock;
|
|
reg sys_pll_lock_sync;
|
|
always @ (posedge pll_clk_o ) sys_pll_lock_sync <= sys_pll_lock;
|
|
|
|
// Dummy register to expand DDR bus to 64 bits
|
|
reg [31:0] nova0_data_extend;
|
|
wire [63:0]nova0_fml_di;
|
|
always @ (posedge mclk_nova0 ) nova0_data_extend <= dis_frame_RAM_din_0;
|
|
assign nova0_fml_di = { nova0_data_extend, dis_frame_RAM_din_0 };
|
|
assign ext_frame_RAM0_data = ext_frame_RAM0_addr[13] ? fml_do_ddr0 [63:32] : fml_do_ddr0 [31:0] ;
|
|
|
|
hpdmc #(
|
|
.csr_addr(4'h0),
|
|
.sdram_depth(14),
|
|
.sdram_columndepth(9)
|
|
) nova0_ddr0 (
|
|
.sys_clk(mclk_nova0),
|
|
.sys_clk_n(!mclk_nova0),
|
|
|
|
.dqs_clk(mclk_nova0),
|
|
.dqs_clk_n(!mclk_nova0),
|
|
|
|
.sys_rst(!reset_n_i),
|
|
|
|
/* Control interface */
|
|
.csr_a(per_addr),
|
|
.csr_we(per_we[0]),
|
|
.csr_di(per_din),
|
|
.csr_do(per_dout_ddr0),
|
|
|
|
/* Simple FML 4x64 interface to the memory contents */
|
|
.fml_adr(ext_frame_RAM0_addr),
|
|
.fml_stb(ext_frame_RAM0_cs_n),
|
|
.fml_we(ext_frame_RAM0_wr),
|
|
.fml_ack(),
|
|
.fml_sel(fml_sel_ddr0),
|
|
.fml_di(nova0_fml_di),
|
|
.fml_do(fml_do_ddr0),
|
|
|
|
/* SDRAM interface.
|
|
* The SDRAM clock should be driven synchronously to the system clock.
|
|
* It is not generated inside this core so you can take advantage of
|
|
* architecture-dependent clocking resources to generate a clean
|
|
* differential clock.
|
|
*/
|
|
.sdram_cke(ddr0_cke_i),
|
|
.sdram_cs_n(ddr0_cs_n_i),
|
|
.sdram_we_n(ddr0_we_n_i),
|
|
.sdram_cas_n(ddr0_cas_n_i),
|
|
.sdram_ras_n(ddr0_ras_n_i),
|
|
.sdram_adr(ddr0_adr_i),
|
|
.sdram_ba(ddr0_ba_i),
|
|
|
|
|
|
.sdram_dm(ddr0_dm_i),
|
|
.sdram_dq(ddr0_dq),
|
|
.sdram_dqs(ddr0_dqs),
|
|
|
|
/* Interface to the DCM generating DQS */
|
|
.dqs_psen(),
|
|
.dqs_psincdec(),
|
|
.dqs_psdone(1'b0),
|
|
|
|
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
|
|
);
|
|
|
|
// DDR port 1
|
|
|
|
// Dummy register to create control signal
|
|
reg [7:0] fml_sel_ddr1;
|
|
always @ (posedge mclk_nova0 )
|
|
begin
|
|
if ( ext_frame_RAM1_cs_n == 1'b0 )
|
|
if ( ext_frame_RAM1_wr )
|
|
fml_sel_ddr1 <= dis_frame_RAM_din_0[23:16];
|
|
else
|
|
fml_sel_ddr1 <= dis_frame_RAM_din_0[31:24];
|
|
end
|
|
assign ext_frame_RAM1_data = ext_frame_RAM1_addr[13] ? fml_do_ddr1 [63:32] : fml_do_ddr1 [31:0] ;
|
|
|
|
hpdmc #(
|
|
.csr_addr(4'h1),
|
|
.sdram_depth(14),
|
|
.sdram_columndepth(9)
|
|
) nova0_ddr1 (
|
|
.sys_clk(mclk_nova0),
|
|
.sys_clk_n(!mclk_nova0),
|
|
|
|
.dqs_clk(mclk_nova0),
|
|
.dqs_clk_n(!mclk_nova0),
|
|
|
|
.sys_rst(!reset_n_i),
|
|
|
|
/* Control interface */
|
|
.csr_a(per_addr),
|
|
.csr_we(per_we[0]),
|
|
.csr_di(per_din),
|
|
.csr_do(per_dout_ddr1),
|
|
|
|
/* Simple FML 4x64 interface to the memory contents */
|
|
.fml_adr(ext_frame_RAM1_addr),
|
|
.fml_stb(ext_frame_RAM1_cs_n),
|
|
.fml_we(ext_frame_RAM1_wr),
|
|
.fml_ack(),
|
|
.fml_sel(fml_sel_ddr1),
|
|
.fml_di(nova0_fml_di),
|
|
.fml_do(fml_do_ddr1),
|
|
|
|
/* SDRAM interface.
|
|
* The SDRAM clock should be driven synchronously to the system clock.
|
|
* It is not generated inside this core so you can take advantage of
|
|
* architecture-dependent clocking resources to generate a clean
|
|
* differential clock.
|
|
*/
|
|
.sdram_cke(ddr1_cke_i),
|
|
.sdram_cs_n(ddr1_cs_n_i),
|
|
.sdram_we_n(ddr1_we_n_i),
|
|
.sdram_cas_n(ddr1_cas_n_i),
|
|
.sdram_ras_n(ddr1_ras_n_i),
|
|
.sdram_adr(ddr1_adr_i),
|
|
.sdram_ba(ddr1_ba_i),
|
|
|
|
|
|
.sdram_dm(ddr1_dm_i),
|
|
.sdram_dq(ddr1_dq),
|
|
.sdram_dqs(ddr1_dqs),
|
|
|
|
/* Interface to the DCM generating DQS */
|
|
.dqs_psen(),
|
|
.dqs_psincdec(),
|
|
.dqs_psdone(1'b0),
|
|
|
|
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
|
|
);
|
|
|
|
// NOVA 1 clock gate
|
|
always @(negedge mclk_i ) enable_nova1 <= power_iso[1];
|
|
AND2_X1_HVT i_nova1_cg (.A1(mclk_i), .A2(enable_nova1), .ZN(mclk_nova1) );
|
|
|
|
|
|
|
|
nova_wrapper nova1 (
|
|
.clk(mclk_nova1),
|
|
.clk_reg(smclk),
|
|
.reset_n(reset_n_i),
|
|
.per_dout(per_dout_nova1),
|
|
.per_addr(per_addr),
|
|
.per_din(per_din[15:0]),
|
|
.per_en(per_en),
|
|
.per_we(per_we),
|
|
.BitStream_buffer_input(BitStream_buffer_input_1_i),
|
|
.BitStream_ram_ren(BitStream_ram_ren_1_i),
|
|
.BitStream_ram_addr(BitStream_ram_addr_1_i),
|
|
.ext_frame_RAM0_cs_n(ext_frame_RAM2_cs_n),
|
|
.ext_frame_RAM0_wr(ext_frame_RAM2_wr),
|
|
.ext_frame_RAM0_addr(ext_frame_RAM2_addr),
|
|
.ext_frame_RAM0_data(ext_frame_RAM2_data),
|
|
.ext_frame_RAM1_cs_n(ext_frame_RAM3_cs_n),
|
|
.ext_frame_RAM1_wr(ext_frame_RAM3_wr),
|
|
.ext_frame_RAM1_addr(ext_frame_RAM3_addr),
|
|
.ext_frame_RAM1_data(ext_frame_RAM3_data),
|
|
.dis_frame_RAM_din(dis_frame_RAM_din_1),
|
|
.power_ack(power_ack[1]),
|
|
.power_control(power_control[1])
|
|
);
|
|
|
|
// DDR port 2
|
|
|
|
// Dummy register to create control signal
|
|
reg [7:0] fml_sel_ddr2;
|
|
always @ (posedge mclk_nova1 )
|
|
begin
|
|
if ( ext_frame_RAM2_cs_n == 1'b0 )
|
|
if ( ext_frame_RAM0_wr )
|
|
fml_sel_ddr2 <= dis_frame_RAM_din_1[7:0];
|
|
else
|
|
fml_sel_ddr2 <= dis_frame_RAM_din_1[15:8];
|
|
end
|
|
// Dummy register to expand DDR bus to 64 bits
|
|
reg [31:0] nova1_data_extend;
|
|
wire [63:0]nova1_fml_di;
|
|
always @ (posedge mclk_nova1 ) nova1_data_extend <= dis_frame_RAM_din_1;
|
|
assign nova1_fml_di = { nova1_data_extend, dis_frame_RAM_din_1 };
|
|
assign ext_frame_RAM2_data = ext_frame_RAM2_addr[13] ? fml_do_ddr2 [63:32] : fml_do_ddr2 [31:0] ;
|
|
|
|
hpdmc #(
|
|
.csr_addr(4'h2),
|
|
.sdram_depth(14),
|
|
.sdram_columndepth(9)
|
|
) nova0_ddr2 (
|
|
.sys_clk(mclk_nova1),
|
|
.sys_clk_n(!mclk_nova1),
|
|
|
|
.dqs_clk(mclk_nova1),
|
|
.dqs_clk_n(!mclk_nova1),
|
|
|
|
.sys_rst(!reset_n_i),
|
|
|
|
/* Control interface */
|
|
.csr_a(per_addr),
|
|
.csr_we(per_we[0]),
|
|
.csr_di(per_din),
|
|
.csr_do(per_dout_ddr2),
|
|
|
|
/* Simple FML 4x64 interface to the memory contents */
|
|
.fml_adr(ext_frame_RAM2_addr),
|
|
.fml_stb(ext_frame_RAM2_cs_n),
|
|
.fml_we(ext_frame_RAM2_wr),
|
|
.fml_ack(),
|
|
.fml_sel(fml_sel_ddr2),
|
|
.fml_di(nova1_fml_di),
|
|
.fml_do(fml_do_ddr2),
|
|
|
|
/* SDRAM interface.
|
|
* The SDRAM clock should be driven synchronously to the system clock.
|
|
* It is not generated inside this core so you can take advantage of
|
|
* architecture-dependent clocking resources to generate a clean
|
|
* differential clock.
|
|
*/
|
|
.sdram_cke(ddr2_cke_i),
|
|
.sdram_cs_n(ddr2_cs_n_i),
|
|
.sdram_we_n(ddr2_we_n_i),
|
|
.sdram_cas_n(ddr2_cas_n_i),
|
|
.sdram_ras_n(ddr2_ras_n_i),
|
|
.sdram_adr(ddr2_adr_i),
|
|
.sdram_ba(ddr2_ba_i),
|
|
|
|
|
|
.sdram_dm(ddr2_dm_i),
|
|
.sdram_dq(ddr2_dq),
|
|
.sdram_dqs(ddr2_dqs),
|
|
|
|
/* Interface to the DCM generating DQS */
|
|
.dqs_psen(),
|
|
.dqs_psincdec(),
|
|
.dqs_psdone(1'b0),
|
|
|
|
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
|
|
);
|
|
|
|
// DDR port 3
|
|
|
|
// Dummy register to create control signal
|
|
reg [7:0] fml_sel_ddr3;
|
|
always @ (posedge mclk_nova1 )
|
|
begin
|
|
if ( ext_frame_RAM3_cs_n == 1'b0 )
|
|
if ( ext_frame_RAM0_wr )
|
|
fml_sel_ddr3 <= dis_frame_RAM_din_1[23:16];
|
|
else
|
|
fml_sel_ddr3 <= dis_frame_RAM_din_1[31:24];
|
|
end
|
|
assign ext_frame_RAM3_data = ext_frame_RAM3_addr[13] ? fml_do_ddr3 [63:32] : fml_do_ddr3 [31:0] ;
|
|
|
|
hpdmc #(
|
|
.csr_addr(4'h1),
|
|
.sdram_depth(14),
|
|
.sdram_columndepth(9)
|
|
) nova0_ddr3 (
|
|
.sys_clk(mclk_nova1),
|
|
.sys_clk_n(!mclk_nova1),
|
|
|
|
.dqs_clk(mclk_nova1),
|
|
.dqs_clk_n(!mclk_nova1),
|
|
|
|
.sys_rst(!reset_n_i),
|
|
|
|
/* Control interface */
|
|
.csr_a(per_addr),
|
|
.csr_we(per_we[0]),
|
|
.csr_di(per_din),
|
|
.csr_do(per_dout_ddr3),
|
|
|
|
/* Simple FML 4x64 interface to the memory contents */
|
|
.fml_adr(ext_frame_RAM3_addr),
|
|
.fml_stb(ext_frame_RAM3_cs_n),
|
|
.fml_we(ext_frame_RAM3_wr),
|
|
.fml_ack(),
|
|
.fml_sel(fml_sel_ddr3),
|
|
.fml_di(nova1_fml_di),
|
|
.fml_do(fml_do_ddr3),
|
|
|
|
/* SDRAM interface.
|
|
* The SDRAM clock should be driven synchronously to the system clock.
|
|
* It is not generated inside this core so you can take advantage of
|
|
* architecture-dependent clocking resources to generate a clean
|
|
* differential clock.
|
|
*/
|
|
.sdram_cke(ddr3_cke_i),
|
|
.sdram_cs_n(ddr3_cs_n_i),
|
|
.sdram_we_n(ddr3_we_n_i),
|
|
.sdram_cas_n(ddr3_cas_n_i),
|
|
.sdram_ras_n(ddr3_ras_n_i),
|
|
.sdram_adr(ddr3_adr_i),
|
|
.sdram_ba(ddr3_ba_i),
|
|
|
|
|
|
.sdram_dm(ddr3_dm_i),
|
|
.sdram_dq(ddr3_dq),
|
|
.sdram_dqs(ddr3_dqs),
|
|
|
|
/* Interface to the DCM generating DQS */
|
|
.dqs_psen(),
|
|
.dqs_psincdec(),
|
|
.dqs_psdone(1'b0),
|
|
|
|
.pll_stat({sys_pll_lock,sys_pll_lock_sync})
|
|
);
|
|
|
|
usb_sys i_usbf (
|
|
// WISHBONE Interface
|
|
// QSG .power_ack(power_ack_2),
|
|
// QSG .power_control(power_control_2),
|
|
.clk_i(mclk_i),
|
|
.rst_i(reset_n_i),
|
|
.wb_addr_i(dmem_addr[17:0]),
|
|
.wb_data_i(per_din),
|
|
.wb_data_o(per_dout_usb),
|
|
.wb_we_i(per_we[0]),
|
|
.wb_stb_i(per_en),
|
|
.inta_o(usb_intb),
|
|
.intb_o(usb_inta),
|
|
|
|
// UTMI Interface
|
|
.phy_clk_pad_i(usb_clk),
|
|
.phy_rst_pad_o(phy_rst_pad),
|
|
.DataOut_pad_o(usb_DataOut),
|
|
.TxValid_pad_o(usb_TxValid),
|
|
.TxReady_pad_i(usb_TxReady),
|
|
|
|
.RxValid_pad_i (usb_RxValid),
|
|
.RxActive_pad_i (usb_RxActive),
|
|
.RxError_pad_i (usb_RxError),
|
|
.DataIn_pad_i (usb_DataIn),
|
|
.LineState_pad_i (usb_LineState)
|
|
);
|
|
|
|
|
|
usb_phy i_usb_phy(
|
|
.clk(usb_clk),
|
|
.rst(phy_rst_pad),
|
|
.phy_tx_mode(1'b0),
|
|
.usb_rst(),
|
|
// UTMI Interface
|
|
.DataOut_i (usb_DataOut),
|
|
.TxValid_i (usb_TxValid),
|
|
.TxReady_o (usb_TxReady),
|
|
.RxValid_o (usb_RxValid),
|
|
.RxActive_o (usb_RxActive),
|
|
.RxError_o (usb_RxError),
|
|
.DataIn_o (usb_DataIn),
|
|
.LineState_o (usb_LineState),
|
|
|
|
.txdp(usb_txdp),
|
|
.txdn(usb_txdn),
|
|
.txoe(usb_txoe),
|
|
.rxd(usb_rxd),
|
|
.rxdp(usb_rxdp),
|
|
.rxdn(usb_rxdn)
|
|
);
|
|
|
|
// --------------------
|
|
// Main PLL
|
|
// DIVR = 1, DIVF = 80. DIVQ = 2
|
|
// Overall Multiply by 40
|
|
// --------------------
|
|
PLL i_MAIN_PLL (
|
|
.REF(lfxt_clk_i), // Reference clock
|
|
.FB(dco_clk), // Feedback clock
|
|
.FSE(1'b1), // Selects source of feedback input
|
|
.BYPASS(1'b0),
|
|
.RESET(!reset_n_i),
|
|
.DIVF7(1'b0), .DIVF6(1'b1), .DIVF5(1'b0), .DIVF4(1'b0), .DIVF3(1'b1), .DIVF2(1'b1), .DIVF1(1'b1), .DIVF0(1'b1),
|
|
.DIVQ2(1'b0), .DIVQ1(1'b0), .DIVQ0(1'b1),
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.DIVR5(1'b0), .DIVR4(1'b0), .DIVR3(1'b0), .DIVR2(1'b0), .DIVR1(1'b0), .DIVR0(1'b0),
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.RANGE2(1'b0), .RANGE1(1'b0), .RANGE0(1'b1),
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|
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.LOCK(sys_pll_lock),
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.PLLOUT(pll_clk_o)
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|
);
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//assign pll_clk = scan_mode_i ? sysclk_byp_i : pll_clk_o;
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MUX2_X2_HVT i_sys_clk_mux ( .A(pll_clk_o), .B(sysclk_byp_i), .S(scan_mode_i), .Z(pll_clk) );
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// --------------------
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// USB PLL
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// DIVR = 1, DIVF = 96. DIVQ = 16
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// Overall Multiply by 6
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// --------------------
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PLL i_USB_PLL (
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.REF(lfxt_clk_i), // Reference clock
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|
.FB(1'b0), // Feedback clock
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.FSE(1'b1), // Selects source of feedback input
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|
.BYPASS(1'b0),
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|
.RESET(!reset_n_i),
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|
.DIVF7(1'b0), .DIVF6(1'b1), .DIVF5(1'b0), .DIVF4(1'b1), .DIVF3(1'b1), .DIVF2(1'b1), .DIVF1(1'b1), .DIVF0(1'b1),
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.DIVQ2(1'b1), .DIVQ1(1'b0), .DIVQ0(1'b0),
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|
.DIVR5(1'b0), .DIVR4(1'b0), .DIVR3(1'b0), .DIVR2(1'b0), .DIVR1(1'b0), .DIVR0(1'b0),
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|
.RANGE2(1'b0), .RANGE1(1'b0), .RANGE0(1'b1),
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|
|
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.LOCK(), // ??? Will it be used?
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|
.PLLOUT(usb_clk_o)
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|
);
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|
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//assign usb_clk = scan_mode_i ? usbclk_byp_i : usb_clk_o;
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MUX2_X2_HVT i_usb_clk_mux ( .A(usb_clk_o), .B(usbclk_byp_i), .S(scan_mode_i), .Z(usb_clk) );
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|
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|
endmodule
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