113 lines
3.6 KiB
Systemverilog
113 lines
3.6 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Bomin Kim
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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`timescale 1ns/1ns
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module alu_tb();
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// Local Signals
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logic[2:0] aluOp;
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logic aluNegAr;
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logic aluBypass;
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logic[31:0] op1;
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logic[31:0] op2;
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logic[31:0] result;
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logic eqFlag;
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// Toplevel instance (DUT)
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alu u_alu (
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.aluOp(aluOp),
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.aluNegAr(aluNegAr),
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.aluBypass(aluBypass),
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.op1(op1),
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.op2(op2),
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.result(result),
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.eqFlag(eqFlag)
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);
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// list of aluOp
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localparam logic[2:0] f3add = 3'b000;
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localparam logic[2:0] f3sl = 3'b001;
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localparam logic[2:0] f3slt = 3'b010;
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localparam logic[2:0] f3sltU = 3'b011;
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localparam logic[2:0] f3xor = 3'b100;
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localparam logic[2:0] f3sr = 3'b101;
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localparam logic[2:0] f3or = 3'b110;
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localparam logic[2:0] f3and = 3'b111;
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// Initialize and run simulation
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initial begin
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dumpWave("wave.vcd");
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// Initialize inputs
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aluOp = 0;
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aluNegAr = 0;
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aluBypass = 0;
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op1 = 0;
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op2 = 0;
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#10
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// Set op1 and op2
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op1 = 32'hDEAD_BEEF; op2 = 32'h0000_0001; #70
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$display("\nTime = %0dns \t : op1 = %h, op2 = %h", $time, op1, op2);
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$display("\nTime = %0dns \t : Is op1 and op2 equal?; eqFlag = %d", $time, eqFlag);
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aluBypass = 1; #70
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$display("\nTime = %0dns \t : AluBypass is set; result = %h", $time, result);
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aluBypass = 0; aluOp = f3add; #70
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$display("\nTime = %0dns \t : Alu operates addition; result = %h", $time, result);
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aluNegAr = 1; #70
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$display("\nTime = %0dns \t : Alu operates subtraction; result = %h", $time, result);
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aluNegAr = 0; aluOp = f3sl; #70
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$display("\nTime = %0dns \t : Alu operates shift left; result = %h", $time, result);
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aluOp = f3slt; #70
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$display("\nTime = %0dns \t : Alu operates set less than; result = %h", $time, result);
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aluOp = f3sltU; #70
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$display("\nTime = %0dns \t : Alu operates set less than (unsigned); result = %h", $time, result);
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aluOp = f3xor; #70
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$display("\nTime = %0dns \t : Alu operates bit-wise XOR; result = %h", $time, result);
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aluOp = f3sr; aluNegAr = 1; #70
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$display("\nTime = %0dns \t : Alu operates arithmetic right shift; result = %h", $time, result);
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aluNegAr = 0; #70
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$display("\nTime = %0dns \t : Alu operates logical right shift; result = %h", $time, result);
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aluOp = f3or; #70
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$display("\nTime = %0dns \t : Alu operates bit-wise OR; result = %h", $time, result);
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aluOp = f3and; #70
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$display("\nTime = %0dns \t : Alu operates bit-wise AND; result = %h", $time, result);
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$finish;
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end
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// Wave Dump Helper Task
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task dumpWave(string fileName);
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// Open wave file and dump all signals (2D arrays not included)
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$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
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$dumpfile(fileName);
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$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "alu_tb");
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$dumpvars(0, alu_tb);
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endtask: dumpWave
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endmodule
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