69 lines
2.0 KiB
Systemverilog
69 lines
2.0 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Bomin Kim
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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`timescale 1ns/1ns
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module pc_tb ();
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// Local Signals
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logic[31:0] CurrentPC;
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logic[31:0] JumpOrBranchPC;
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logic JumpOrBranch;
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logic[31:0] NextPC;
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logic reset;
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logic clk;
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// Toplevel instance (DUT)
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pc u_pc (
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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.NextPC(NextPC),
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.reset(reset),
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.clk(clk)
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);
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// Clock generation
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always #20 clk = ~clk;
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// Initialization and run simulation
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initial begin
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dumpWave("wave.vcd");
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clk = 0;
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JumpOrBranchPC = 32'h8;
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JumpOrBranch = 0;
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reset = 0; #100;
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reset = 1; #100;
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reset = 0; #490;
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JumpOrBranch = 1; #60;
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JumpOrBranch = 0; #500;
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$finish;
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end
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// NextPC Monitor
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initial begin
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$monitor("time=%0t clk=%b reset=%b JumpOrBranch=%0h CurrentPC=%0h NextPC=%0h", $time, clk, reset, JumpOrBranch, CurrentPC, NextPC);
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end
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// Wave Dump Helper Task
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task dumpWave(string fileName);
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// Open wave file and dump all signals (2D arrays not included)
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$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
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$dumpfile(fileName);
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$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "pc_tb");
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$dumpvars(0, pc_tb);
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endtask: dumpWave
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endmodule
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