138 lines
4.2 KiB
Systemverilog
138 lines
4.2 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Bomin Kim
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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`timescale 1ns/1ns
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module reg_file_tb ();
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// Local Signals
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logic[4:0] Rs1;
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logic[4:0] Rs2;
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logic[4:0] Rd;
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logic[31:0] RRs1;
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logic[31:0] RRs2;
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logic[31:0] WRd;
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logic WrReg;
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logic reset;
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logic clk;
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// Toplevel instance (DUT)
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reg_file u_reg_file (
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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.reset(reset),
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.clk(clk)
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);
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// Clock generation
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always #20 clk = ~clk;
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// Initialization and run simulation
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initial begin
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dumpWave("wave.vcd");
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// Initialize inputs
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clk = 0;
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Rs1 = 0; Rs2 = 0; Rd = 0;
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WRd = 0; WrReg = 0; // Read
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reset = 1;
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#50
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reset = 0;
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#50 // Write 0xDEADBEEF to reg21
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Rd = 5'd21;
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WrReg = 1; // Write
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WRd = 32'hDEADBEEF;
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#50; WrReg = 0;
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#50
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Rs1 = 5'd21; // read reg21 into RRs1
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Rs2 = 5'd0;
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#50 // Write 0x12345678 to reg5
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Rd = 5'd5;
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WrReg = 1; // Write
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WRd = 32'h12345678;
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#50; WrReg = 0;
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#50
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Rs1 = 5'd5; // read reg10 into RRs1
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#50
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Rs1 = 5'd0; // read zero register
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#50
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Rd = 5'd0; // attempt to write 0xCAFEBABE to zero register
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WRd = 32'hCAFEBABE;
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WrReg = 1; // Write
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#50; WrReg = 0;
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#50
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Rs1 = 5'd5; // Read from reg5
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#200
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$finish;
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end
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// Wave Dump Helper Task
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task dumpWave(string fileName);
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// Open wave file and dump all signals (2D arrays not included)
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$display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName);
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$dumpfile(fileName);
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$display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "reg_file_tb");
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$dumpvars(0, reg_file_tb);
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// Dump registers in wave file
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$display("\nTime = %0dns \t : Dumping Registers in wave file", $time);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[1]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[2]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[3]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[4]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[5]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[6]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[7]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[8]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[9]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[10]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[11]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[12]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[13]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[14]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[15]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[16]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[17]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[18]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[19]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[20]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[21]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[22]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[23]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[24]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[25]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[26]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[27]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[28]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[29]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[30]);
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$dumpvars(0, reg_file_tb.u_reg_file.registers[31]);
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endtask: dumpWave
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endmodule
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