61 lines
1.4 KiB
Systemverilog
Executable File
61 lines
1.4 KiB
Systemverilog
Executable File
module MemGen_32_11 #(
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parameter data_width = 32,
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parameter addr_width = 11,
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parameter mem_depth = 2048
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)(
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input chip_en,
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input clock,
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input [addr_width-1:0]addr,
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output reg [data_width-1:0]rd_data,
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input rd_en,
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input wr_en,
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input [data_width-1:0]wr_data
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);
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// Bank selection: 1 bit selects one of 2 banks
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reg [1:0] mem_sel ;
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wire [31:0] mem_data_out [1:0];
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// Address decoder and output multiplexer
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always @(*)
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begin
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if ( chip_en == 1'b1 )
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case (addr[10])
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1'b0 : begin mem_sel = 2'b01; rd_data = mem_data_out[0]; end
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1'b1 : begin mem_sel = 2'b10; rd_data = mem_data_out[1]; end
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endcase
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else
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begin
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mem_sel = 2'b00;
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rd_data = 32'h00000000;
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end
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end
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genvar i;
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// Instantiate 2 banks, each with 2 halves (low + high 16 bits)
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generate
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for (i = 0; i < 2; i = i + 1) begin
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MemGen_16_10 U_lo (
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.chip_en(mem_sel[i]),
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.clock(clock),
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.addr(addr[9:0]),
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.rd_en(rd_en),
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.rd_data(mem_data_out[i][15:0]),
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.wr_en(wr_en),
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.wr_data(wr_data[15:0])
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);
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MemGen_16_10 U_hi (
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.chip_en(mem_sel[i]),
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.clock(clock),
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.addr(addr[9:0]),
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.rd_en(rd_en),
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.rd_data(mem_data_out[i][31:16]),
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.wr_en(wr_en),
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.wr_data(wr_data[31:16])
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);
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end
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endgenerate
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endmodule
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