592 lines
65 KiB
Plaintext
592 lines
65 KiB
Plaintext
*******************************************************************
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* Oasys-RTL™ - release 2022.2.R1 *
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* *
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* This material contains trade secrets or otherwise confidential *
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* information owned by Siemens Industry Software Inc. or its *
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* affiliates (collectively, "SISW"), or its licensors. Access to *
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* and use of this information is strictly limited as set forth *
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* in the Customer’s applicable agreements with SISW. *
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* *
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* Unpublished work. © 2023 Siemens *
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* *
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* Program : ../bin/Linux-x86_64-O/oasysGui *
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* Version : 22.2-p002 *
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* Date : Mon Jan 16 21:36:23 PST 2023 *
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* Build : releases/22.2-54756.0-CentOS_6.5-O *
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*******************************************************************
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config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft
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loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap
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checked out license: psyncore
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date : Thu May 28 13:29:15 CEST 2026
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ppid/pid : 2451524/2451534
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hostname : efiapps0.ads1.fh-nuernberg.de
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arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64
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install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1
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currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl
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logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.01
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tmpdir : /tmp/oasys.2451524/
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> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl
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> source scripts_risc_v/1_read_design.tcl
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> source scripts_risc_v/init_design.tcl
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> config_shell -echo true
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> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain}
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> source scripts_risc_v/demo_chip_design_files.tcl
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-----------------------------
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Done setting design variables
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-----------------------------
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> read_db ./libs/nangate_mvt.odb
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info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/nangate_mvt.odb' [UFILE-107]
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starting at 00:00:00(cpu)/0:00:51(wall) 102MB(vsz)/470MB(peak)
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extracting odb ... finished at 00:00:00(cpu)/0:00:51(wall) 102MB(vsz)/470MB(peak)
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Write Date : Mon, 21 Jun 2021 13:47:25 -0700
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Host : orw-ericc-r78 (64bit)
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Tool Version : 21.1-p004 (60,9-71,11)
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Tool Date : Fri Jun 11 12:44:10 PDT 2021
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Tool Build : 52545.0-O
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Design Name :
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Comment :
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loading environment ... finished at 00:00:00(cpu)/0:00:51(wall) 102MB(vsz)/470MB(peak)
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loading libraries ... finished at 00:00:01(cpu)/0:00:51(wall) 113MB(vsz)/476MB(peak)
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all done
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> create_threshold_voltage_group HVT -lib_cells {NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI33_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X4_HVT ...(34 more)}
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> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)}
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> create_threshold_voltage_group LVT -lib_cells {NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/ANTENNA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X3_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/HA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC0_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC1_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI33_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X4_LVT ...(34 more)}
|
||
> report_operating_conditions
|
||
Report Operating conditions:
|
||
-----+---------------+--------+-------------+------------------------------------+--------+--------+-----------
|
||
|Name |Default?|Type |Library |Process |Voltage |Temperature
|
||
-----+---------------+--------+-------------+------------------------------------+--------+--------+-----------
|
||
1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000
|
||
2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000
|
||
3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000
|
||
4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000
|
||
5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000
|
||
-----+---------------+--------+-------------+------------------------------------+--------+--------+-----------
|
||
> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false
|
||
> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl
|
||
info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126]
|
||
info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126]
|
||
info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126]
|
||
info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126]
|
||
info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126]
|
||
info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126]
|
||
info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126]
|
||
> set_max_route_layer 10
|
||
Top-most available layer for routing set to metal10
|
||
> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false
|
||
|
||
-----------------------------
|
||
|
||
Done preparing design for synthesis
|
||
|
||
-----------------------------
|
||
|
||
> source scripts_risc_v/2_synthesize_optimize.tcl
|
||
> synthesize -module cpu -map_to_scan -gate_clock
|
||
starting synthesize at 00:00:01(cpu)/0:00:56(wall) 120MB(vsz)/480MB(peak)
|
||
warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215]
|
||
warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215]
|
||
-------> Message [NL-215] suppressed 44 times
|
||
info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112]
|
||
info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113]
|
||
info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111]
|
||
info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400]
|
||
info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400]
|
||
info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400]
|
||
info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401]
|
||
info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401]
|
||
info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400]
|
||
warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218]
|
||
info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401]
|
||
info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400]
|
||
info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401]
|
||
warning: named parameter override 'MEM_INIT_FILE' does not match any parameter in module 'main_mem' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/cpu.sv:122)[8]) [VLOG-409]
|
||
info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400]
|
||
info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400]
|
||
info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401]
|
||
warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112]
|
||
warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102]
|
||
-------> Message [POWER-102] suppressed 22 times
|
||
info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401]
|
||
info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401]
|
||
finished synthesize at 00:00:02(cpu)/0:00:57(wall) 173MB(vsz)/530MB(peak)
|
||
> set_route_layer_max_usage metal2 0.5
|
||
> set_route_layer_max_usage metal3 0.8
|
||
> set_route_layer_max_usage metal6 0.8
|
||
> write_db ./output/odb/riscv_chip.syn.odb
|
||
info: design 'cpu' has no physical info [WRITE-120]
|
||
warning: WrSdc.. design 'cpu' has no timing constraints [TA-118]
|
||
> read_sdc -verbose ./constraints/riscv.sdc
|
||
> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz
|
||
> create_generated_clock -name clk_12p5 -source clk_25mhz -divide_by 2 thePC/clk
|
||
info: create_generated_clock attempted to push hier assertion to driver but driver drives other loads
|
||
info: Moved 1 constraints on hierarchical pins to their respective driving/loading pins:
|
||
thePC/clk to {thePC/CurrentPC_reg[0]/CK} {thePC/CurrentPC_reg[1]/CK} {thePC/CurrentPC_reg[2]/CK} {thePC/CurrentPC_reg[3]/CK} {thePC/CurrentPC_reg[4]/CK} {thePC/CurrentPC_reg[5]/CK} {thePC/CurrentPC_reg[6]/CK} {thePC/CurrentPC_reg[7]/CK} {thePC/CurrentPC_reg[8]/CK} {thePC/CurrentPC_reg[9]/CK} {thePC/CurrentPC_reg[10]/CK} {thePC/CurrentPC_reg[11]/CK} {thePC/CurrentPC_reg[12]/CK} {thePC/CurrentPC_reg[13]/CK} {thePC/CurrentPC_reg[14]/CK} {thePC/CurrentPC_reg[15]/CK} {thePC/CurrentPC_reg[16]/CK} {thePC/CurrentPC_reg[17]/CK} {thePC/CurrentPC_reg[18]/CK} {thePC/CurrentPC_reg[19]/CK} {thePC/CurrentPC_reg[20]/CK} {thePC/CurrentPC_reg[21]/CK} {thePC/CurrentPC_reg[22]/CK} {thePC/CurrentPC_reg[23]/CK} {thePC/CurrentPC_reg[24]/CK} {thePC/CurrentPC_reg[25]/CK} {thePC/CurrentPC_reg[26]/CK} {thePC/CurrentPC_reg[27]/CK} {thePC/CurrentPC_reg[28]/CK} {thePC/CurrentPC_reg[29]/CK} {thePC/CurrentPC_reg[30]/CK} {thePC/CurrentPC_reg[31]/CK}
|
||
> set_clock_uncertainty -setup 0.5 clk_25mhz
|
||
> set_clock_uncertainty -hold 0.2 clk_25mhz
|
||
> set_clock_transition 0.1 clk_25mhz
|
||
> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] }
|
||
> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] }
|
||
> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
|
||
> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
|
||
> set_false_path -from btn[0]
|
||
# set_false_path -from btn[0]
|
||
> set_clock_groups -asynchronous -group clk_25mhz -group clk_12p5
|
||
> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] }
|
||
> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
|
||
> current_design
|
||
> set_max_fanout 20 cpu
|
||
> current_design
|
||
> set_max_transition 0.5 cpu
|
||
info: 'set_max_fanout' command ignored 1 time(s) [SDC-148]
|
||
info: 'set_max_transition' command ignored 1 time(s) [SDC-150]
|
||
> report_design_metrics
|
||
Report Physical info:
|
||
------------------------+--------+-----------+------------
|
||
| |Area (squm)|Leakage (uW)
|
||
------------------------+--------+-----------+------------
|
||
Design Name |cpu | |
|
||
Total Instances | 7271| 60170| 625.907
|
||
Macros | 4| 46249| 518.216
|
||
Pads | 0| 0| 0.000
|
||
Phys | 0| 0| 0.000
|
||
Blackboxes | 0| 0| 0.000
|
||
Cells | 7267| 13921| 107.691
|
||
Buffers | 0| 0| 0.000
|
||
Inverters | 645| 343| 4.523
|
||
Clock-Gates | 32| 111| 0.688
|
||
Combinational | 5426| 6457| 51.156
|
||
Latches | 32| 85| 0.602
|
||
FlipFlops | 1132| 6926| 50.722
|
||
Single-Bit FF | 1132| 6926| 50.722
|
||
Multi-Bit FF | 0| 0| 0.000
|
||
Clock-Gated | 993| |
|
||
Bits | 1132| 6926| 50.722
|
||
Load-Enabled | 0| |
|
||
Clock-Gated | 993| |
|
||
Tristate Pin Count | 0| |
|
||
Physical Info |Unplaced| |
|
||
Chip Size (mm x mm) | | 0|
|
||
Fixed Cell Area | | 0|
|
||
Phys Only | 0| 0|
|
||
Placeable Area | | 0|
|
||
Movable Cell Area | | 60170|
|
||
Utilization (%) | | |
|
||
Chip Utilization (%) | | |
|
||
Total Wire Length (mm)| 0.000| |
|
||
Longest Wire (mm) | | |
|
||
Average Wire (mm) | | |
|
||
------------------------+--------+-----------+------------
|
||
> check_timing
|
||
Report Check Timing:
|
||
-----+------------------------------+------+--------+------+-----------------------------------------------
|
||
|Item |Errors|Warnings|Status|Description
|
||
-----+------------------------------+------+--------+------+-----------------------------------------------
|
||
1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design
|
||
2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock
|
||
3 |unconstrained_IO | 0| 1|Passed|Unconstrained IO pin
|
||
4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion
|
||
5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data
|
||
6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data
|
||
7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving
|
||
8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals
|
||
9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal
|
||
10 |clock_pin_with_data | 0| 2|Passed|Clock pin has data signal arriving
|
||
-----+------------------------------+------+--------+------+-----------------------------------------------
|
||
> all_inputs
|
||
> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz scan_en }
|
||
# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz scan_en
|
||
> all_inputs
|
||
> all_outputs
|
||
> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz scan_en } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
|
||
# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz scan_en -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]}
|
||
> all_outputs
|
||
> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] }
|
||
# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]}
|
||
> report_path_groups
|
||
Report Path Groups:
|
||
-----+-------+------+---------+---------
|
||
| Path |Weight|Critical |Worst
|
||
| Group | |Range(ps)|Slack(ps)
|
||
-----+-------+------+---------+---------
|
||
1 |default| 1.000| 0.0| 17832.1
|
||
2 |I2R | 1.000| 0.0| 39366.0
|
||
3 |I2O | 1.000| 0.0|<ill>
|
||
4 |R2O | 1.000| 0.0| 36153.7
|
||
-----+-------+------+---------+---------
|
||
> optimize -virtual
|
||
starting optimize at 00:00:03(cpu)/0:00:59(wall) 181MB(vsz)/530MB(peak)
|
||
info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s)
|
||
Log file for child PID=2452026: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w1.01.log
|
||
Log file for child PID=2452034: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w2.01.log
|
||
Log file for child PID=2452043: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w3.01.log
|
||
Log file for child PID=2452053: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w4.01.log
|
||
info: optimized '<TOP>' area changed 0.0squm (x1), total 13919.5squm (#1, 0 secs)
|
||
info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146]
|
||
info: optimized 'cpu__GC0' area changed -1461.7squm (x1), total 12457.8squm (#2)
|
||
info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11616.8squm (#3)
|
||
info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11533.2squm (#4)
|
||
info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11442.8squm (#5)
|
||
info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11440.4squm (#6)
|
||
info: optimized '<TOP>' area changed 0.0squm (x1), total 11440.4squm (#7, 0 secs)
|
||
info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11440.4squm (#8)
|
||
info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11440.4squm (#9)
|
||
info: optimized '<TOP>' area changed 0.0squm (x1), total 11440.4squm (#10, 0 secs)
|
||
done optimizing area at 00:00:15(cpu)/0:01:06(wall) 181MB(vsz)/568MB(peak)
|
||
Splitting congested rtl-partitions
|
||
info: Target library/cell information has changed that further may change timing results. [TA-159]
|
||
info: optimizing design 'cpu' - propagating constants
|
||
info: optimized '<TOP>' area changed 0.0squm (x1), total 11440.4squm (#1, 0 secs)
|
||
info: set slack mode to optimize shift
|
||
info: resetting all path groups
|
||
info: activated path group default @ 18015.8ps
|
||
info: activated path group I2R @ 39177.7ps
|
||
info: suspended path group I2O @ <ill>ps
|
||
info: activated path group R2O @ 36338.3ps
|
||
info: finished path group default @ 18015.8ps
|
||
info: finished path group R2O @ 36338.3ps
|
||
info: finished path group I2R @ 39177.7ps
|
||
info: reactivating path groups
|
||
info: reactivated path group default @ 18015.8ps
|
||
info: reactivated path group I2R @ 39177.7ps
|
||
info: reactivated path group R2O @ 36338.3ps
|
||
info: finished path group default @ 18015.8ps
|
||
info: finished path group R2O @ 36338.3ps
|
||
info: finished path group I2R @ 39177.7ps
|
||
info: set slack mode to normal
|
||
info: done with all path groups
|
||
info: restore all path groups
|
||
info: starting area recovery on module cpu
|
||
info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.03 secs
|
||
info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs
|
||
info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs
|
||
info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs
|
||
info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs
|
||
info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs)
|
||
done optimizing virtual at 00:00:17(cpu)/0:01:07(wall) 200MB(vsz)/568MB(peak)
|
||
finished optimize at 00:00:17(cpu)/0:01:07(wall) 201MB(vsz)/568MB(peak)
|
||
> write_db ./output/odb/riscv_chip.virtual_opt.odb
|
||
> report_timing
|
||
Report for group default
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Startpoint: theMem/IRData_reg[18]/Q
|
||
(Clocked by clk_25mhz R)
|
||
Endpoint: theMem/mem_addr_reg[5]/D
|
||
(Clocked by clk_25mhz F)
|
||
Path Group: default
|
||
Data required time: 19227.4
|
||
(Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6)
|
||
Data arrival time: 1211.5
|
||
Slack: 18015.8
|
||
Logic depth: 46
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Arrival Arc Net Net Total fan-
|
||
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
|
||
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 2
|
||
i_0_1_2/B->Z MUX2_X2_LVT rr 0.0 0.0 0.0 0.0 100.0 0.0 0.0 100
|
||
theMem/IRData_reg[18]/CK->Q
|
||
SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11
|
||
theRegisters/i_1_0_1371/A->ZN
|
||
INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3
|
||
theRegisters/i_1_0_1339/A2->ZN
|
||
NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4
|
||
theRegisters/i_1_0_1321/A2->ZN
|
||
NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32
|
||
theRegisters/i_1_0_722/B1->ZN
|
||
AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1
|
||
theRegisters/i_1_0_721/A->ZN
|
||
INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1
|
||
theRegisters/i_1_0_718/A->ZN
|
||
AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1
|
||
theRegisters/i_1_0_716/A3->ZN
|
||
NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1
|
||
theRegisters/i_1_0_715/A->ZN
|
||
AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1
|
||
theRegisters/i_1_0_704/A2->ZN
|
||
NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3
|
||
theDecoder/i_0_133/C2->ZN
|
||
AOI222_X4_LVT fr 428.1 110.5 110.5 0.0 12.2 0.8 23.5 1
|
||
theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7
|
||
theDecoder/theALU/i_0_706/B1->ZN
|
||
OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2
|
||
theDecoder/theALU/i_0_705/A->ZN
|
||
INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1
|
||
theDecoder/theALU/i_0_42/A->ZN
|
||
OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1
|
||
theDecoder/theALU/i_0_40/C1->ZN
|
||
AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1
|
||
theDecoder/theALU/i_0_39/B->ZN
|
||
AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1
|
||
theDecoder/theALU/i_0_38/B2->ZN
|
||
OAI222_X2_LVT rf 555.7 16.9 16.9 0.0 27.7 0.9 2.9 1
|
||
theDecoder/theALU/i_0_37/C2->ZN
|
||
AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1
|
||
theDecoder/theALU/i_0_35/B1->ZN
|
||
OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1
|
||
theDecoder/theALU/i_0_34/A->ZN
|
||
INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1
|
||
theDecoder/theALU/i_0_33/A->ZN
|
||
AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1
|
||
theDecoder/theALU/i_0_32/C2->ZN
|
||
OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1
|
||
theDecoder/theALU/i_0_31/A->ZN
|
||
OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1
|
||
theDecoder/theALU/i_0_28/B1->ZN
|
||
AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1
|
||
theDecoder/theALU/i_0_27/A->ZN
|
||
AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1
|
||
theDecoder/theALU/i_0_26/B->ZN
|
||
AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1
|
||
theDecoder/theALU/i_0_25/B2->ZN
|
||
OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1
|
||
theDecoder/theALU/i_0_24/C2->ZN
|
||
AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1
|
||
theDecoder/theALU/i_0_23/A->ZN
|
||
AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1
|
||
theDecoder/theALU/i_0_22/A->ZN
|
||
AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1
|
||
theDecoder/theALU/i_0_21/A->ZN
|
||
AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1
|
||
theDecoder/theALU/i_0_20/C2->ZN
|
||
OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1
|
||
theDecoder/theALU/i_0_19/A->ZN
|
||
OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1
|
||
theDecoder/theALU/i_0_18/B2->ZN
|
||
AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1
|
||
theDecoder/theALU/i_0_17/B2->ZN
|
||
OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1
|
||
theDecoder/theALU/i_0_16/A->ZN
|
||
OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1
|
||
theDecoder/theALU/i_0_13/B1->ZN
|
||
AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1
|
||
theDecoder/theALU/i_0_12/A4->ZN
|
||
NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1
|
||
theDecoder/theALU/i_0_0/A3->ZN
|
||
OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2
|
||
theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1
|
||
theDecoder/i_0_113/B1->ZN
|
||
AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1
|
||
theDecoder/i_0_111/A2->ZN
|
||
AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1
|
||
theDecoder/i_0_110/A2->ZN
|
||
NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13
|
||
i_0_1_63/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3
|
||
theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1
|
||
theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1
|
||
theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Report for group I2R
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Startpoint: scan_en
|
||
(Clocked by rtDefaultClock R)
|
||
Endpoint: clk12p5_reg/D
|
||
(Clocked by clk_25mhz R)
|
||
Path Group: I2R
|
||
Data required time: 39223.7
|
||
(Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 276.3)
|
||
Data arrival time: 46.0
|
||
Slack: 39177.7
|
||
Logic depth: 2
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Arrival Arc Net Net Total fan-
|
||
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
|
||
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
scan_en {input_arrival} f 0.0 0.0 0.0 6.9 12.6 2
|
||
i_0_1_1/A2->ZN NAND2_X4_LVT fr 7.0 7.0 7.0 0.0 0.0 0.7 2.8 1
|
||
clk12p5_reg_enable_mux_0/S->Z
|
||
MUX2_X1_LVT rf 46.0 38.9 38.9 0.0 4.9 0.8 1.9 1
|
||
clk12p5_reg/D SDFF_X1_LVT f 46.0 0.0 0.0 6.6
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Report for group I2O
|
||
Report for group R2O
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Startpoint: theMem/IRData_reg[18]/Q
|
||
(Clocked by clk_25mhz R)
|
||
Endpoint: led[7]
|
||
(Clocked by clk_25mhz R)
|
||
Path Group: R2O
|
||
Data required time: 37500.0
|
||
(Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0)
|
||
Data arrival time: 1161.7
|
||
Slack: 36338.3
|
||
Logic depth: 44
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
Arrival Arc Net Net Total fan-
|
||
Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location
|
||
(ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um)
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 2
|
||
i_0_1_2/B->Z MUX2_X2_LVT rr 0.0 0.0 0.0 0.0 100.0 0.0 0.0 100
|
||
theMem/IRData_reg[18]/CK->Q
|
||
SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11
|
||
theRegisters/i_1_0_1371/A->ZN
|
||
INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3
|
||
theRegisters/i_1_0_1339/A2->ZN
|
||
NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4
|
||
theRegisters/i_1_0_1321/A2->ZN
|
||
NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32
|
||
theRegisters/i_1_0_722/B1->ZN
|
||
AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1
|
||
theRegisters/i_1_0_721/A->ZN
|
||
INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1
|
||
theRegisters/i_1_0_718/A->ZN
|
||
AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1
|
||
theRegisters/i_1_0_716/A3->ZN
|
||
NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1
|
||
theRegisters/i_1_0_715/A->ZN
|
||
AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1
|
||
theRegisters/i_1_0_704/A2->ZN
|
||
NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3
|
||
theDecoder/i_0_133/C2->ZN
|
||
AOI222_X4_LVT fr 428.1 110.5 110.5 0.0 12.2 0.8 23.5 1
|
||
theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7
|
||
theDecoder/theALU/i_0_706/B1->ZN
|
||
OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2
|
||
theDecoder/theALU/i_0_705/A->ZN
|
||
INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1
|
||
theDecoder/theALU/i_0_42/A->ZN
|
||
OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1
|
||
theDecoder/theALU/i_0_40/C1->ZN
|
||
AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1
|
||
theDecoder/theALU/i_0_39/B->ZN
|
||
AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1
|
||
theDecoder/theALU/i_0_38/B2->ZN
|
||
OAI222_X2_LVT rf 555.7 16.9 16.9 0.0 27.7 0.9 2.9 1
|
||
theDecoder/theALU/i_0_37/C2->ZN
|
||
AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1
|
||
theDecoder/theALU/i_0_35/B1->ZN
|
||
OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1
|
||
theDecoder/theALU/i_0_34/A->ZN
|
||
INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1
|
||
theDecoder/theALU/i_0_33/A->ZN
|
||
AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1
|
||
theDecoder/theALU/i_0_32/C2->ZN
|
||
OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1
|
||
theDecoder/theALU/i_0_31/A->ZN
|
||
OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1
|
||
theDecoder/theALU/i_0_28/B1->ZN
|
||
AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1
|
||
theDecoder/theALU/i_0_27/A->ZN
|
||
AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1
|
||
theDecoder/theALU/i_0_26/B->ZN
|
||
AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1
|
||
theDecoder/theALU/i_0_25/B2->ZN
|
||
OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1
|
||
theDecoder/theALU/i_0_24/C2->ZN
|
||
AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1
|
||
theDecoder/theALU/i_0_23/A->ZN
|
||
AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1
|
||
theDecoder/theALU/i_0_22/A->ZN
|
||
AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1
|
||
theDecoder/theALU/i_0_21/A->ZN
|
||
AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1
|
||
theDecoder/theALU/i_0_20/C2->ZN
|
||
OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1
|
||
theDecoder/theALU/i_0_19/A->ZN
|
||
OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1
|
||
theDecoder/theALU/i_0_18/B2->ZN
|
||
AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1
|
||
theDecoder/theALU/i_0_17/B2->ZN
|
||
OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1
|
||
theDecoder/theALU/i_0_16/A->ZN
|
||
OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1
|
||
theDecoder/theALU/i_0_13/B1->ZN
|
||
AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1
|
||
theDecoder/theALU/i_0_12/A4->ZN
|
||
NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1
|
||
theDecoder/theALU/i_0_0/A3->ZN
|
||
OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2
|
||
theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1
|
||
theDecoder/i_0_113/B1->ZN
|
||
AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1
|
||
theDecoder/i_0_111/A2->ZN
|
||
AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1
|
||
theDecoder/i_0_110/A2->ZN
|
||
NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13
|
||
i_0_1_63/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3
|
||
led[7] f 1161.7 0.0 0.0 10.2
|
||
--------------------------------------------------------------------------------------------------------------------------------------
|
||
> report_path_groups
|
||
Report Path Groups:
|
||
-----+-------+------+---------+---------
|
||
| Path |Weight|Critical |Worst
|
||
| Group | |Range(ps)|Slack(ps)
|
||
-----+-------+------+---------+---------
|
||
1 |default| 1.000| 0.0| 18015.8
|
||
2 |I2R | 1.000| 0.0| 39177.7
|
||
3 |I2O | 1.000| 0.0|<ill>
|
||
4 |R2O | 1.000| 0.0| 36338.3
|
||
-----+-------+------+---------+---------
|
||
|
||
-------------------------------------
|
||
|
||
Synthesis and optimization complete
|
||
|
||
-------------------------------------
|
||
|
||
INFO::Running oasys Tessent DFT flow
|
||
> source scripts_risc_v/oasys_tessent_dft.tcl
|
||
INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow
|
||
> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent
|
||
> define_test_clock -pin clk_25mhz
|
||
> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable
|
||
> set_dont_scan theMem true
|
||
> define_test_pin -name reset -pin {btn[0]} -scan_mode 1
|
||
> set_dont_scan clk12p5_reg true
|
||
invalid command name "add_input_constraints"
|
||
while executing
|
||
"add_input_constraints scan_en -C1"
|
||
(file "scripts_risc_v/oasys_tessent_dft.tcl" line 43)
|
||
invoked from within
|
||
"tcl_source scripts_risc_v/oasys_tessent_dft.tcl"
|
||
invalid command name "add_input_constraints"
|
||
while executing
|
||
"add_input_constraints scan_en -C1"
|
||
(file "scripts_risc_v/oasys_tessent_dft.tcl" line 43)
|
||
invoked from within
|
||
"tcl_source scripts_risc_v/oasys_tessent_dft.tcl"
|
||
("uplevel" body line 1)
|
||
invoked from within
|
||
"uplevel 2 [list tcl_source $resolvedFilePath]"
|
||
(procedure "rt::sourceFile" line 31)
|
||
invoked from within
|
||
"rt::sourceFile false false {} scripts_risc_v/oasys_tessent_dft.tcl"
|
||
("eval" body line 1)
|
||
invoked from within
|
||
"eval $cmd"
|
||
invoked from within
|
||
"source scripts_risc_v/oasys_tessent_dft.tcl"
|
||
invoked from within
|
||
"if {[info exists dft_flow] && [string match $dft_flow tessent]} {
|
||
puts "INFO::Running oasys Tessent DFT flow"
|
||
source scripts_risc_v/oasys_tessent_..."
|
||
(file "scripts_risc_v/2_synthesize_optimize.tcl" line 97)
|
||
invoked from within
|
||
"tcl_source scripts_risc_v/2_synthesize_optimize.tcl"
|