45 lines
1.4 KiB
Systemverilog
45 lines
1.4 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 Bomin Kim Added reset handling condition
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// *********************************************************************************************
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module reg_file (
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input logic[4:0] Rs1,
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input logic[4:0] Rs2,
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input logic[4:0] Rd,
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output logic[31:0] RRs1,
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output logic[31:0] RRs2,
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input logic[31:0] WRd,
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input logic WrReg,
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input logic reset,
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input logic clk
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);
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// Define the registers array
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logic[31:0] registers[31:1];
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// Register file reading
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assign RRs1 = Rs1 == 0 ? '0 : registers[Rs1];
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assign RRs2 = Rs2 == 0 ? '0 : registers[Rs2];
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// Register file writing
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always_ff @(posedge clk) begin
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if (reset) begin
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for (int i=1; i<32; i++)
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registers[i] <= '0;
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end else begin
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if (WrReg & Rd != 0) registers[Rd] <= WRd;
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end
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end
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endmodule
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