68 lines
1.8 KiB
Verilog
Executable File
68 lines
1.8 KiB
Verilog
Executable File
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// --------------------------------------------------
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// Simple CPU writable register
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// Outputs can be used to control power down signals
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// --------------------------------------------------
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module powerdown_control (
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input clk,
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input reset_n,
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//---register access---
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input [13:0] per_addr,
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input [31:0] per_din,
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input per_en,
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input per_we,
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input per_rd,
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input [31:0] power_ack,
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output reg [31:0] per_dout,
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output reg [31:0] power_control,
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output reg [31:0] power_iso
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);
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parameter [13:0] BASE_ADDR = 14'h400;
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always @(posedge clk or negedge reset_n)
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begin
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if ( reset_n == 1'b0 )
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begin
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power_control = 32'h00000000;
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power_iso = 32'h00000000;
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end
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else
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begin
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// Write reg
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if ( per_en == 1'b1 && per_we == 1'b0 && per_addr[13:4] == BASE_ADDR[13:4])
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begin
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case (per_addr[3:0])
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4'h0 : power_control = per_din;
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4'h1 : power_iso = per_din;
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endcase
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end
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end
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end
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// read_reg
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always @(*)
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begin
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if ( per_en == 1'b1 && per_rd == 1'b1 && per_addr[13:4] == BASE_ADDR[13:4])
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begin
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case (per_addr[3:0])
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4'h0 : per_dout = power_control;
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4'h1 : per_dout = power_iso;
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4'h2 : per_dout = power_ack;
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default : per_dout = 32'h00000000;
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endcase
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end
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else
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per_dout = 32'h00000000;
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end
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endmodule
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