116 lines
2.8 KiB
Verilog
Executable File
116 lines
2.8 KiB
Verilog
Executable File
module usb_sys (// WISHBONE Interface
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clk_i, rst_i,
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wb_addr_i, wb_data_i, wb_data_o,
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wb_we_i, wb_stb_i, inta_o, intb_o,
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// UTMI Interface
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phy_clk_pad_i, phy_rst_pad_o,
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DataOut_pad_o, TxValid_pad_o, TxReady_pad_i,
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RxValid_pad_i, RxActive_pad_i, RxError_pad_i,
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// QSG DataIn_pad_i, LineState_pad_i, power_control, power_ack
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DataIn_pad_i, LineState_pad_i
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);
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//QSG input power_control;
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//QSG output power_ack;
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input clk_i;
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input rst_i;
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input [17:0] wb_addr_i;
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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input wb_we_i;
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input wb_stb_i;
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output inta_o;
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output intb_o;
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input phy_clk_pad_i;
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output phy_rst_pad_o;
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output [7:0] DataOut_pad_o;
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output TxValid_pad_o;
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input TxReady_pad_i;
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input [7:0] DataIn_pad_i;
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input RxValid_pad_i;
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input RxActive_pad_i;
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input RxError_pad_i;
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input [1:0] LineState_pad_i;
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wire [13:0] usb_buf_addr;
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wire [31:0] usb_buf_dout;
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wire [31:0] usb_buf_din;
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wire usb_buf_wen;
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wire usb_buf_ren;
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usbf_top i_usbf (
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//QSG .power_control(power_control),
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//QSG .power_ack(power_ack),
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// WISHBONE Interface
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.clk_i(clk_i),
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.rst_i(rst_i),
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.wb_addr_i(wb_addr_i),
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.wb_data_i(wb_data_i),
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.wb_data_o(wb_data_o),
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.wb_ack_o(),
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.wb_we_i(wb_we_i),
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.wb_stb_i(wb_stb_i),
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.wb_cyc_i(1'b0),
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.inta_o(inta_o),
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.intb_o(intb_o),
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.dma_req_o(),
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.dma_ack_i(16'b0),
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.susp_o(),
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.resume_req_i(1'b0),
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// UTMI Interface
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.phy_clk_pad_i(phy_clk_pad_i),
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.phy_rst_pad_o(phy_rst_pad_o),
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.DataOut_pad_o(DataOut_pad_o),
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.TxValid_pad_o(TxValid_pad_o),
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.TxReady_pad_i(TxReady_pad_i),
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.RxValid_pad_i (RxValid_pad_i),
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.RxActive_pad_i (RxActive_pad_i),
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.RxError_pad_i (RxError_pad_i),
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.DataIn_pad_i (DataIn_pad_i),
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.XcvSelect_pad_o (),
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.TermSel_pad_o (),
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.SuspendM_pad_o (),
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.LineState_pad_i (LineState_pad_i),
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.OpMode_pad_o(),
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.usb_vbus_pad_i(1'b0),
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.VControl_Load_pad_o(),
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.VControl_pad_o(),
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.VStatus_pad_i(8'b0),
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// Buffer Memory Interface
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.sram_adr_o(usb_buf_addr),
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.sram_data_i(usb_buf_dout),
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.sram_data_o(usb_buf_din),
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.sram_re_o(usb_buf_ren),
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.sram_we_o(usb_buf_wen)
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);
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MemGen_32_14 usb_buffer_mem (
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.chip_en(1'b1),
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.clock(clk_i),
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.addr(usb_buf_addr),
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.rd_data(usb_buf_dout),
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.rd_en(usb_buf_ren),
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.wr_data(usb_buf_din),
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.wr_en(usb_buf_wen )
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);
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endmodule
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