61 lines
1.0 KiB
Verilog
Executable File
61 lines
1.0 KiB
Verilog
Executable File
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module IDDR2 #(
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parameter DDR_ALIGNMENT = "NONE",
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parameter INIT_Q0 = 1'b0,
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parameter INIT_Q1 = 1'b0,
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parameter SRTYPE = "SYNC"
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)
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(Q0, Q1, C0, C1, CE, D, R, S);
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output reg Q0;
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output reg Q1;
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input C0;
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input C1;
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input CE;
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input D;
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input R;
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input S;
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always @(posedge C0 or posedge R ) begin
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if (R)
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Q0 <= 1'b0;
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else
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if (CE)
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Q0 <= D;
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end
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always @(posedge C1 or posedge R ) begin
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if (R)
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Q1 <= 1'b0;
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else
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if (CE)
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Q1 <= D;
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end
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endmodule // IDDR2
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module ODDR2 #(
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parameter DDR_ALIGNMENT = "NONE",
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parameter INIT = 1'b0,
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parameter SRTYPE = "SYNC"
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)(Q, C0, C1, CE, D0, D1, R, S);
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output Q;
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input C0;
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input C1;
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input CE;
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input D0;
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input D1;
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input R;
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input S;
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wire data_0, data_1;
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assign data_0 = ( C0 && CE ) ? D0 : 1'b0;
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assign data_1 = ( C1 && CE ) ? D1 : 1'b0;
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assign Q = data_0 || data_1;
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endmodule // ODDR2
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