DfT/libs/MemGen_16_10.memlib
2026-05-29 10:19:13 +02:00

36 lines
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Core (MemGen_16_10) {
Memory {
Port (clock) {
Function = Clock;
}
Port (chip_en) {
Function = Select;
Polarity = activeHigh;
}
Port (rd_en) {
Function = ReadEnable;
Polarity = activeHigh;
}
Port (wr_en) {
Function = WriteEnable;
Polarity = activeHigh;
}
Port (addr[9:0]) {
Function = Address;
}
Port (wr_data[15:0]) {
Function = Data;
Direction = Input;
}
Port (rd_data[15:0]) {
Function = Data;
Direction = Output;
}
AddressCounter {
Function (address) {
CountRange = [0 1023];
}
}
}
}