136 lines
3.3 KiB
Systemverilog
136 lines
3.3 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 H.Elzomor Renamed file and module from soc to cpu
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// 15.Oct.2025 H.Elzomor Added an initial condition for clk_12p5
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// *********************************************************************************************
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module cpu (
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output logic[7:0] led,
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input logic[6:0] btn,
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input logic clk_25mhz
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//input logic scan_en
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);
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// Local Signals
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// Clock & Reset
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logic clk;
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// logic clk12p5;
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logic reset;
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// PC
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logic[31:0] CurrentPC;
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logic[31:0] JumpOrBranchPC;
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logic JumpOrBranch;
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logic[31:0] NextPC;
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// Memory
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logic[31:0] DAddr;
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logic[31:0] WData;
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logic[31:0] RData;
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logic[31:0] Instruction;
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logic WrMem;
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logic[1:0] DWidth;
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// Register File;
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logic[4:0] Rs1;
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logic[4:0] Rs2;
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logic[4:0] Rd;
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logic[31:0] RRs1;
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logic[31:0] RRs2;
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logic[31:0] WRd;
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logic WrReg;
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// Protection
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logic Illegal;
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// Logic
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assign clk = clk_25mhz;
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// Clock (12.5MHz)
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//assign clk = scan_en ? clk_25mhz : clk12p5;
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//assign clk = clk12p5;
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// always_ff @(posedge clk_25mhz) begin
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// if (reset)
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// clk12p5 <= 1'b0;
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// else if (!scan_en)
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// clk12p5 <= ~clk12p5;
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// end
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// Reset
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assign reset = ~btn[0];
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// LED
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assign led[0] = Illegal;
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assign led[1] = WrMem;
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assign led[7:2] = NextPC[7:2];
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// Module Instantiation
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// Decoder
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decoder theDecoder (
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// PC
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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// Memory
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.DAddr(DAddr),
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.WData(WData),
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.RData(RData),
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.Instruction(Instruction),
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.WrMem(WrMem),
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.DWidth(DWidth),
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// Register File
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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// Protection
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.Illegal(Illegal)
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);
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// Register File
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reg_file theRegisters (
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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.reset(reset),
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.clk(clk)
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);
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// PC
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pc thePC (
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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.NextPC(NextPC),
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.reset(reset),
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.clk(clk)
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);
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// Main Memory
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main_mem #(
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) theMem (
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.DAddr(DAddr),
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.IAddr(NextPC),
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.DWData(WData),
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.DRData(RData),
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.IRData(Instruction),
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.DWE(WrMem),
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.DWidth(DWidth),
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.reset(reset),
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.clk(clk)
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);
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endmodule
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