143 lines
4.9 KiB
Systemverilog
143 lines
4.9 KiB
Systemverilog
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Aliakbar Merchant [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- ---------- -------------------------------------------------
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// 22.Oct.2025 A.Merchant Added reset handling condition for Instr. read logic
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// 22.Oct.2025 A.Merchant Added reset handling condition for data write logic
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// *********************************************************************************************
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`default_nettype wire
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module main_mem #(
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parameter int ABits = 13 // Number of address bits
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//parameter string MEM_INIT_FILE = "" // Optional memory initializations file
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) (
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input logic clk, // Clock
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input logic reset, // Active high sync reset
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input logic[31:0] DAddr, // Data Address
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input logic[31:0] IAddr, // Instruction Address
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input logic[31:0] DWData, // Data to write
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output logic[31:0] DRData, // Data read
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output logic[31:0] IRData, // Instruction read
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input logic DWE, // Data write enable, 1=Write
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input logic [1:0] DWidth // Access width (byte, half word, word)
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);
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// Local Parameter
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localparam logic[1:0] _byte = 2'b00; // byte: 8 bits
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localparam logic[1:0] _half = 2'b01; // half: 16 bits
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localparam logic[1:0] _word = 2'b10; // word: 32 bits
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// Local Signals
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//logic[31:0] RAM[2**(ABits-2)-1:0]; // Memory array 8KB(8192): ignores lowest 2 bits as 32bit-word
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logic [31:0] irTmp;
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logic[31:0] drTmp; // Temporary register to hold the data read from RAM.
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logic [10:0] mem_addr; // 11-bit word address for MemGen_32_11
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logic [31:0] mem_wdata; // 32-bit data bus for MemGen_32_11
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logic [31:0] mem_rdata; // 32-bit data bus for MemGen_32_11
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MemGen_32_11 RAM (
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.chip_en (1'b1),
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.clock (clk),
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.addr (mem_addr),
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.rd_en (!DWE),
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.rd_data (mem_rdata),
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.wr_en (DWE),
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.wr_data (mem_wdata)
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);
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// memory initilizations
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// initial begin
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//if (MEM_INIT_FILE != "") begin
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// $readmemh(MEM_INIT_FILE, RAM);
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// end
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// end
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//---------------------------------------------------------------------------//
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//--------------------------- DATA WRITE LOGIC ---------------------------//
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//---------------------------------------------------------------------------//
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always_ff @(negedge clk) begin
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if (reset) begin
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mem_addr <= 0;
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end else begin
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if (DWE) begin
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mem_addr <= DAddr[(ABits-1):2];
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// RAM[DAddr[(ABits-1):2]] <= DWData;
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case (DWidth)
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_word:
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mem_wdata <= DWData;
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_half:
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case (DAddr[1])
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1'b0: mem_wdata [31:16] <= DWData[15:0];
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1'b1: mem_wdata [15: 0] <= DWData[15:0];
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endcase
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_byte:
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case (DAddr[1:0])
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2'b00: mem_wdata [31:24] <= DWData[7:0];
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2'b01: mem_wdata [23:16] <= DWData[7:0];
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2'b10: mem_wdata [15: 8] <= DWData[7:0];
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2'b11: mem_wdata [ 7: 0] <= DWData[7:0];
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endcase
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default: ;
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endcase
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end else begin
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mem_addr <= IAddr[(ABits-1):2];
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end
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end
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end
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//---------------------------------------------------------------------------//
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//--------------------------- DATA READ LOGIC ----------------------------//
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//---------------------------------------------------------------------------//
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always_ff @(negedge clk) begin
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drTmp <= mem_rdata;
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end
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always_comb begin
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case (DWidth)
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_word:
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DRData = drTmp;
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_half:
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case (DAddr[1])
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1'b0: DRData = {16'b0, drTmp[31:16]};
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1'b1: DRData = {16'b0, drTmp[15: 0]};
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endcase
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_byte:
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case (DAddr[1:0])
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2'b00: DRData = {24'b0, drTmp[31:24]};
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2'b01: DRData = {24'b0, drTmp[23:16]};
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2'b10: DRData = {24'b0, drTmp[15: 8]};
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2'b11: DRData = {24'b0, drTmp[ 7: 0]};
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endcase
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default: ;
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endcase
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end
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//---------------------------------------------------------------------------//
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//----------------------- INSTRUCTION READ LOGIC -------------------------//
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//---------------------------------------------------------------------------//
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//
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//fetch intrcution from memory into IRData
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always_ff @(posedge clk) begin
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if (reset) begin
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IRData <= mem_rdata;
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end
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else begin
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IRData <= mem_rdata;
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end
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end
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endmodule
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