19 lines
794 B
Forth
19 lines
794 B
Forth
// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Aug.2025 by Marcus Bednara
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// Last Modified : 01.Nov.2025 by Hussein Elzomor
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// ------
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// Notes : All ${}-variables must be provided by shell or Makefile {using export}
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// *********************************************************************************************
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// Used with other compilers and simulators (eg. Icarus)
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hw/dv/rtl/pc_tb.sv
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hw/dv/rtl/reg_file_tb.sv
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hw/dv/rtl/alu_tb.sv
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hw/dv/rtl/main_mem_tb.sv
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hw/dv/rtl/decoder_tb.sv
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hw/dv/rtl/cpu_tb.sv
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