76 lines
2.4 KiB
Tcl
Executable File
76 lines
2.4 KiB
Tcl
Executable File
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#########################################################
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# 1_load_design.tcl
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#
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# Description: Load the design input files into
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# Oasys-RTL and set design
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# conditions. Must be run after the
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# init_design.tcl script
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#
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# Usage: source in Oasys-RTL Command prompt
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#
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# Dependencies: init_design.tcl
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# Launched from Oasys-RTL shell
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#
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#########################################################
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#set script_dir [file dirname [info script]]
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set script_dir "scripts_risc_v"
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set ekit_dir [file dirname ${script_dir}]
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#Check if dependent scripts have been loaded
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if {![info exists top_module]} {
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source ${script_dir}/init_design.tcl
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}
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#=======================================================#
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#Load technology libraries (Liberty and LEF)
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#=======================================================#
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# Read Oasys libraries (ODB)
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read_db ${ekit_dir}/libs/nangate_mvt.odb
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#foreach vt [list hvt svt lvt] {
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foreach vt [list svt] {
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set vtUC [string toupper $vt]
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set lib_cells(${vt}) [get_lib_cells *${vtUC}*]
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if { [sizeof_collection $lib_cells(${vt})] > 0 } {
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create_threshold_voltage_group ${vtUC} -lib_cells $lib_cells($vt)
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}
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}
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report_operating_conditions
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#=======================================================#
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#Config the tolerance level for RTL parser for elobration
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#=======================================================#
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config_tolerance -blackbox true -connection_mismatch true \
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-missing_physical_library true \
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-continue_on_error false
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#=======================================================#
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#Read verilog design files
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#=======================================================#
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if {[file exists ${ekit_dir}/riscv_rtl/hw/rtl/alu.sv]} {
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read_verilog -sv $rtl_list -include $search_path
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}
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#=======================================================#
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#Set design-specific parameters before synthesis
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#=======================================================#
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#Set the max routing layer (defined in 1_init_design.tcl)
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set_max_route_layer $max_route_layer
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#Reset dont_use property on all lib cells
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set_dont_use [get_lib_cell * ] false
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#Specify clock gating options
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#set_clock_gating_options -control_point before \
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-minimum_bitwidth 4 -sequential_cell latch
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echo "\n-----------------------------"
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echo "\nDone preparing design for synthesis"
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echo "\n-----------------------------\n"
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