library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.reg32.all; use work.task.all; entity add is port ( clk : in std_logic; reset : in std_logic; task_start : in std_logic; task_state : out work.task.State; signal_a_read : out std_logic; signal_a_readdata : in std_logic_vector(31 downto 0); signal_b_read : out std_logic; signal_b_readdata : in std_logic_vector(31 downto 0); signal_write : out std_logic; signal_writedata : out std_logic_vector(31 downto 0) ); end entity add; architecture rtl of add is ------------------------------------------------------------------------- -- äußere Task-FSM ------------------------------------------------------------------------- signal current_task_state : work.task.State; signal next_task_state : work.task.State; signal index : integer range 0 to work.task.STREAM_LEN; ------------------------------------------------------------------------- -- innere Add-FSM ------------------------------------------------------------------------- type AddState is ( ADD_IDLE, -- wartet auf run_calc ADD_REQ_SAMPLES, -- Read anfordern ADD_WAIT_DATA, -- einen Takt warten, bis FIFO-Daten gültig sind ADD_START, -- FIFO-Daten latches + float_add starten ADD_WAIT_DONE, -- auf done vom float_add warten ADD_WRITE -- Ergebnis in Senke schreiben ); signal current_add_state : AddState; signal next_add_state : AddState; -- float_add-Schnittstelle signal start_calc : std_logic; signal add_done : std_logic; signal result_sum : std_logic_vector(31 downto 0); -- Operanden-Register für den Addierer signal op_a_reg : std_logic_vector(31 downto 0); signal op_b_reg : std_logic_vector(31 downto 0); -- Task läuft UND es sind noch Werte zu berechnen signal run_calc : std_logic; begin ------------------------------------------------------------------------- -- float_add mit registrierten Operanden instanzieren ------------------------------------------------------------------------- u_float_add : entity work.float_add port map ( clk => clk, reset => reset, start => start_calc, A => op_a_reg, B => op_b_reg, done => add_done, sum => result_sum ); ------------------------------------------------------------------------- -- äußere Task-State-Maschine ------------------------------------------------------------------------- task_state_transitions : process ( current_task_state, task_start, index ) is begin next_task_state <= current_task_state; case current_task_state is when work.task.TASK_IDLE => if task_start = '1' then next_task_state <= work.task.TASK_RUNNING; end if; when work.task.TASK_RUNNING => -- wenn letztes Sample geschrieben wurde -> DONE if index = work.task.STREAM_LEN then next_task_state <= work.task.TASK_DONE; end if; when work.task.TASK_DONE => if task_start = '1' then next_task_state <= work.task.TASK_RUNNING; end if; end case; end process task_state_transitions; -- Task läuft UND es sind noch Werte zu berechnen run_calc <= '1' when (current_task_state = work.task.TASK_RUNNING and index < work.task.STREAM_LEN) else '0'; ------------------------------------------------------------------------- -- innere Add-FSM: kombinatorischer Teil ------------------------------------------------------------------------- add_state_transitions : process ( current_add_state, run_calc, add_done, index ) is begin next_add_state <= current_add_state; case current_add_state is when ADD_IDLE => if run_calc = '1' then next_add_state <= ADD_REQ_SAMPLES; end if; when ADD_REQ_SAMPLES => -- Read-Impuls, Daten stehen im nächsten Takt an next_add_state <= ADD_WAIT_DATA; when ADD_WAIT_DATA => -- jetzt liegen die neuen FIFO-Werte stabil an, -- im nächsten Zustand werden sie gelatcht + Addition gestartet next_add_state <= ADD_START; when ADD_START => -- Addierer starten, dann auf done warten next_add_state <= ADD_WAIT_DONE; when ADD_WAIT_DONE => if add_done = '1' then next_add_state <= ADD_WRITE; end if; when ADD_WRITE => if index = work.task.STREAM_LEN then next_add_state <= ADD_IDLE; else next_add_state <= ADD_REQ_SAMPLES; end if; end case; end process add_state_transitions; ------------------------------------------------------------------------- -- synchroner Prozess: Zustände + tatsächliche Ausgänge ------------------------------------------------------------------------- sync : process ( clk, reset ) is begin if reset = '1' then current_task_state <= work.task.TASK_IDLE; current_add_state <= ADD_IDLE; index <= 0; signal_a_read <= '0'; signal_b_read <= '0'; signal_write <= '0'; signal_writedata <= (others => '0'); start_calc <= '0'; op_a_reg <= (others => '0'); op_b_reg <= (others => '0'); elsif rising_edge(clk) then -- Zustände übernehmen current_task_state <= next_task_state; current_add_state <= next_add_state; -- Default-Ausgänge pro Takt signal_a_read <= '0'; signal_b_read <= '0'; signal_write <= '0'; start_calc <= '0'; case current_task_state is when work.task.TASK_IDLE => -- beim Warten Index zurücksetzen index <= 0; when work.task.TASK_RUNNING => case current_add_state is when ADD_IDLE => null; when ADD_REQ_SAMPLES => -- neuen Wert aus beiden FIFOs anfordern signal_a_read <= '1'; signal_b_read <= '1'; -- FIFO-Daten latches und Addierer starten op_a_reg <= signal_a_readdata; op_b_reg <= signal_b_readdata; when ADD_WAIT_DATA => -- nur warten, bis FIFO-Daten stabil sind null; when ADD_START => start_calc <= '1'; -- Start HIGH when ADD_WAIT_DONE => -- Berechnung läuft weiter -> Start HIGH lassen, -- bis add_done='1' ist start_calc <= '1'; when ADD_WRITE => -- Ergebnis schreiben und Index erhöhen signal_write <= '1'; signal_writedata <= result_sum; index <= index + 1; end case; when work.task.TASK_DONE => null; end case; end if; end process sync; task_state <= current_task_state; end architecture rtl;