235 lines
7.9 KiB
VHDL
235 lines
7.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity add is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_a_read : out std_logic;
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signal_a_readdata : in std_logic_vector(31 downto 0);
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signal_b_read : out std_logic;
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signal_b_readdata : in std_logic_vector(31 downto 0);
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector(31 downto 0)
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);
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end entity add;
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architecture rtl of add is
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-------------------------------------------------------------------------
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-- äußere Task-FSM
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-------------------------------------------------------------------------
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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-------------------------------------------------------------------------
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-- innere Add-FSM
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-------------------------------------------------------------------------
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type AddState is (
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ADD_IDLE, -- wartet auf run_calc
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ADD_REQ_SAMPLES, -- Read anfordern
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ADD_WAIT_DATA, -- einen Takt warten, bis FIFO-Daten gültig sind
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ADD_START, -- FIFO-Daten latches + float_add starten
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ADD_WAIT_DONE, -- auf done vom float_add warten
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ADD_WRITE -- Ergebnis in Senke schreiben
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);
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signal current_add_state : AddState;
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signal next_add_state : AddState;
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-- float_add-Schnittstelle
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signal start_calc : std_logic;
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signal add_done : std_logic;
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signal result_sum : std_logic_vector(31 downto 0);
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-- Operanden-Register für den Addierer
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signal op_a_reg : std_logic_vector(31 downto 0);
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signal op_b_reg : std_logic_vector(31 downto 0);
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-- Task läuft UND es sind noch Werte zu berechnen
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signal run_calc : std_logic;
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begin
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-------------------------------------------------------------------------
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-- float_add mit registrierten Operanden instanzieren
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-------------------------------------------------------------------------
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u_float_add : entity work.float_add
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port map (
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clk => clk,
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reset => reset,
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start => start_calc,
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A => op_a_reg,
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B => op_b_reg,
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done => add_done,
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sum => result_sum
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);
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-------------------------------------------------------------------------
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-- äußere Task-State-Maschine
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-------------------------------------------------------------------------
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if task_start = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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-- wenn letztes Sample geschrieben wurde -> DONE
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if index = work.task.STREAM_LEN then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if task_start = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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-- Task läuft UND es sind noch Werte zu berechnen
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run_calc <= '1' when (current_task_state = work.task.TASK_RUNNING
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and index < work.task.STREAM_LEN)
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else '0';
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-------------------------------------------------------------------------
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-- innere Add-FSM: kombinatorischer Teil
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-------------------------------------------------------------------------
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add_state_transitions : process ( current_add_state, run_calc, add_done, index ) is
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begin
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next_add_state <= current_add_state;
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case current_add_state is
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when ADD_IDLE =>
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if run_calc = '1' then
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next_add_state <= ADD_REQ_SAMPLES;
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end if;
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when ADD_REQ_SAMPLES =>
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-- Read-Impuls, Daten stehen im nächsten Takt an
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next_add_state <= ADD_WAIT_DATA;
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when ADD_WAIT_DATA =>
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-- jetzt liegen die neuen FIFO-Werte stabil an,
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-- im nächsten Zustand werden sie gelatcht + Addition gestartet
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next_add_state <= ADD_START;
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when ADD_START =>
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-- Addierer starten, dann auf done warten
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next_add_state <= ADD_WAIT_DONE;
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when ADD_WAIT_DONE =>
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if add_done = '1' then
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next_add_state <= ADD_WRITE;
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end if;
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when ADD_WRITE =>
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if index = work.task.STREAM_LEN then
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next_add_state <= ADD_IDLE;
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else
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next_add_state <= ADD_REQ_SAMPLES;
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end if;
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end case;
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end process add_state_transitions;
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-------------------------------------------------------------------------
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-- synchroner Prozess: Zustände + tatsächliche Ausgänge
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-------------------------------------------------------------------------
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sync : process ( clk, reset ) is
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begin
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if reset = '1' then
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current_task_state <= work.task.TASK_IDLE;
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current_add_state <= ADD_IDLE;
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index <= 0;
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signal_a_read <= '0';
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signal_b_read <= '0';
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signal_write <= '0';
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signal_writedata <= (others => '0');
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start_calc <= '0';
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op_a_reg <= (others => '0');
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op_b_reg <= (others => '0');
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elsif rising_edge(clk) then
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-- Zustände übernehmen
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current_task_state <= next_task_state;
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current_add_state <= next_add_state;
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-- Default-Ausgänge pro Takt
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signal_a_read <= '0';
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signal_b_read <= '0';
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signal_write <= '0';
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start_calc <= '0';
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case current_task_state is
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when work.task.TASK_IDLE =>
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-- beim Warten Index zurücksetzen
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index <= 0;
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when work.task.TASK_RUNNING =>
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case current_add_state is
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when ADD_IDLE =>
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null;
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when ADD_REQ_SAMPLES =>
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-- neuen Wert aus beiden FIFOs anfordern
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signal_a_read <= '1';
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signal_b_read <= '1';
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-- FIFO-Daten latches und Addierer starten
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op_a_reg <= signal_a_readdata;
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op_b_reg <= signal_b_readdata;
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when ADD_WAIT_DATA =>
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-- nur warten, bis FIFO-Daten stabil sind
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null;
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when ADD_START =>
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start_calc <= '1'; -- Start HIGH
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when ADD_WAIT_DONE =>
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-- Berechnung läuft weiter -> Start HIGH lassen,
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-- bis add_done='1' ist
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start_calc <= '1';
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when ADD_WRITE =>
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-- Ergebnis schreiben und Index erhöhen
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signal_write <= '1';
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signal_writedata <= result_sum;
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index <= index + 1;
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end case;
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when work.task.TASK_DONE =>
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null;
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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