import myhdl
from myhdl import *

@block
def counter_4bit(clk, rst, data, updown, load, data_out):

    @always(clk.posedge)
    def cycle():
        if rst:
            data_out.next = 0
        elif load:
            data_out.next = data
        else:
            if updown:
                data_out.next = data_out + 1
            else:
                data_out.next = data_out - 1

    return cycle


def convert():
    clk = Signal(bool(0))
    rst = Signal(bool(0)) # nur sync reset hier
    # reset = ResetSignal(0, active=0, isasync=True)
    updown = Signal(bool(0))
    load = Signal(bool(0))
    data = Signal(modbv(val=0, min=0, max=15)[4:])
    data_out = Signal(modbv(val=0, min=0, max=15)[4:])

    inst = counter_4bit(clk, rst, data, updown, load, data_out)
    inst.convert(hdl='Verilog')
    # inst.convert(hdl='VHDL')
