`include "bcd_to_7seg.v"   


module digit_driver
#(
   parameter D = 28'd0
)
(
   input clk, input [19:0] number, input dot, output [7:0] segs, output [4:0] digs
);

    // io for 7seg
    reg [2:0] active_digit;
    wire [4:0] buf_digs;

    wire [19:0] number;
    wire [3:0] a_number;
    wire [6:0] seg_out;

    bcd_to_7seg bcd_to_7seg_inst(
        .bcd_in(a_number), 
        .seg_out(seg_out)
    );

    // see bcd_to_7seg.v for segments placement
    // common anode ~seg_out[], common cathode seg_out[]
    
    assign segs = { dot, seg_out };

    assign buf_digs = (number > 20'hFFFF) ? 5'b11111 :
                    (number > 20'hFFF) ? 5'b01111 :
                    (number > 20'hFF) ? 5'b00111 :
                    (number > 20'hF) ? 5'b00011 :
                    5'b00001; // default shouldn't happen

    assign digs = buf_digs & (1'b1 << active_digit);
    assign a_number = (number & (4'b1111 << (active_digit*4))) >> (active_digit*4);

    always @(posedge clk)
    begin
        active_digit <= active_digit + 1'b1;
        if(active_digit > 3'd3)
            active_digit <= 1'b0;
    end



endmodule