diff --git a/4-bit-counter-cocotb/tests/Makefile b/4-bit-counter-cocotb/tests/Makefile
index 8359ad6..190a467 100644
--- a/4-bit-counter-cocotb/tests/Makefile
+++ b/4-bit-counter-cocotb/tests/Makefile
@@ -32,7 +32,7 @@ TOPLEVEL_LANG ?= verilog
 PWD=$(shell pwd)
 
 ifeq ($(TOPLEVEL_LANG),verilog)
-    VERILOG_SOURCES = $(PWD)/../hdl/counter.sv
+    VERILOG_SOURCES = $(PWD)/../hdl/counter.v
 else ifeq ($(TOPLEVEL_LANG),vhdl)
     VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl
 else