module tb_counter_4bit;

reg clk;
reg rst;
reg [3:0] data;
reg updown;
reg load;
wire [3:0] data_out;



initial begin
    $from_myhdl(
        clk,
        rst,
        data,
        updown,
        load
    );
    $to_myhdl(
        data_out
    );
    
    // dump file
    $dumpfile("tb_counter_4bit.lxt");
    $dumpvars(0, tb_counter_4bit);
end

counter_4bit dut(
    clk,
    rst,
    data,
    updown,
    load,
    data_out
);

endmodule