`include "digit_driver.v" `include "pwm.v" `include "clocks.v" `include "counter.v" // A verilog module transforms a 4-bit number into a displayable 7-bit value. // This number is incremented every ~0.25sec. module top( input clk, output LED_R, output LED_G, output LED_B, output seg_b, output seg_a, output seg_f, output seg_g, output seg_d, output seg_e, output seg_c, output seg_p, input [3:0] SW, output dig_1, output dig_2, output dig_3, output dig_4, output dig_5 ); wire clk_pwm; wire clk_7seg; wire clk_counter; clocks #(.PRE_PWM(28'd12), .PRE_7SEG(28'd12000), .PRE_COUNTER(28'd12000)) clocks_inst ( .clk(clk), .clk_pwm(clk_pwm), .clk_7seg(clk_7seg), .clk_counter(clk_counter) ); wire rst; wire updown; wire load; reg [19:0] data = 20'h1337; wire [19:0] data_out; assign rst = SW[0]; assign updown = SW[1]; assign load = SW[2]; counter TIM1 ( .clk(clk_counter), .rst(rst), .data(data), .updown(updown), .load(load), .data_out(data_out) ); wire pwm_en_write; assign pwm_en_write = SW[3]; wire [7:0] pwm_brightness; reg [7:0] led_brightness; assign pwm_brightness = led_brightness; wire pwm_out; pwm pwm_inst(.clk(clk_pwm), .en(pwm_en_write), .value_input(pwm_brightness), .out(pwm_out)); // active low, color white assign LED_R = ~pwm_out; assign LED_G = ~pwm_out; assign LED_B = ~pwm_out; wire [19:0] number; assign number = data_out; assign dot = rst; wire [7:0] segs; assign seg_a = segs[0]; assign seg_b = segs[1]; assign seg_c = segs[2]; assign seg_d = segs[3]; assign seg_e = segs[4]; assign seg_f = segs[5]; assign seg_g = segs[6]; assign seg_p = segs[7]; wire [4:0] digs; assign dig_1 = digs[0]; assign dig_2 = digs[1]; assign dig_3 = digs[2]; assign dig_4 = digs[3]; assign dig_5 = digs[4]; digit_driver dig_inst(.clk(clk_7seg), .number(number), .dot(dot), .segs(segs), .digs(digs)); initial begin led_brightness = 10; end endmodule