signal_processing_vorlage/hardware/signal_processing/sine.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.float.all;
    use work.task.all;

entity sine is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        step_size : in work.reg32.word;
        phase : in work.reg32.word;
        amplitude : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity sine;

architecture rtl of sine is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

	type CalcState is (
		CALC_IDLE,
		CALC_READ,
		CALC_PROCESS,	
		CALC_WRITE
	);
	signal Calc_State : CalcState;

	signal data_valid_ipcore : std_logic;
	signal busy_ipcore : std_logic;
	signal result_valid_ipcore : std_logic;

	signal phase_ipcore : signed(31 downto 0); 
	signal sine_ipcore : signed(31 downto 0);

	
begin
	u_float_sine: entity work.float_sine
		generic map(
			ITERATIONS => 8
		)
		port map(
			clk => clk,
			reset => reset,

			data_valid => data_valid_ipcore,
			busy => busy_ipcore,
			result_valid => result_valid_ipcore,
			-- " TODO Check if this is allowed (direkt access to maped signal)"
			angle => phase_ipcore,
			sine => sine_ipcore
		);

    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
                signal_write <= '0';
            when work.task.TASK_RUNNING =>
                index <= index + 1;
                signal_write <= '1';
                signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                index <= 0;
                signal_write <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;
	phase_ipcore <= (SIGNED(phase));

end architecture rtl;