Loesung des Praktikums Systementwurf
- Bjarne Hoesch
- Bernhard Schoeffel
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- component pll_main is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X'; -- reset
- outclk_0 : out std_logic; -- clk
- locked : out std_logic -- export
- );
- end component pll_main;
-
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