signal_processing_vorlage/tests/hardware/task_crc/Makefile

vhdl_srcs = ../../../hardware/system/reg32.vhd \
            ../../../hardware/system/task.vhd \
            ../../../hardware/system/avalon_slave.vhd \
            ../../../hardware/system/avalon_slave_transitions.vhd \
            ../../../hardware/system/float.vhd \
            ../../../hardware/system/hardware_task_control.vhd \
            ../../../hardware/system/data_channel_control.vhd \
            ../../../hardware/system/data_sink_mux.vhd \
            ../../../hardware/system/data_source_mux.vhd \
            ../../../hardware/system/fifo.vhd \
            ../../../hardware/system/data_channel.vhd \
            ../../../hardware/signal_processing/crc.vhd \
            ../../../hardware/system/task_crc.vhd \
            ../test_utility.vhd \
            ../test_avalon_slave.vhd \
            ../test_hardware_task.vhd \
            ../test_data_channel.vhd \
            ../../data/fft.vhd \
            ../../data/crc.vhd \
            test_task_crc.vhd \

main = test_task_crc
expected_data = ../../data/crc.py

CHECK_RESULTS = true

include ../vhdl.mk