signal_processing_vorlage/hardware/system/hardware_task.vhd

library ieee;
    use ieee.std_logic_1164.all;

entity hardware_task is
    port (
        clk : in std_logic;
        reset : in std_logic;

        ctrl_address : in std_logic_vector( 3 downto 0 );
        ctrl_read : in std_logic;
        ctrl_readdata : out std_logic_vector( 31 downto 0 );
        ctrl_write : in std_logic;
        ctrl_writedata : in std_logic_vector( 31 downto 0 );

        task_address : out std_logic_vector( 3 downto 0 );
        task_read : out std_logic;
        task_readdata : in std_logic_vector( 31 downto 0 );
        task_write : out std_logic;
        task_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity hardware_task;

architecture rtl of hardware_task is
begin
    task_address <= ctrl_address;
    task_read <= ctrl_read;
    ctrl_readdata <= task_readdata;
    task_write <= ctrl_write;
    task_writedata <= ctrl_writedata;
end architecture rtl;