signal_processing_vorlage/hardware/system/avalon_slave.vhd

library ieee;
    use ieee.std_logic_1164.all;

package avalon_slave is

    type State is (
        SLAVE_IDLE,
        SLAVE_READ,
        SLAVE_READ_DATA,
        SLAVE_WRITE
    );

    type Request is record
        address : std_logic_vector( 3 downto 0 );
        read : std_logic;
        write : std_logic;
        writedata : std_logic_vector( 31 downto 0 );
    end record Request;

    type Response is record
        readdata : std_logic_vector( 31 downto 0 );
    end record Response;

end package avalon_slave;