Started implementing Task Sine in vhdl

hardware/signal_processing/sine.vhd

@@ -30,7 +30,39 @@ architecture rtl of sine is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	type CalcState is (
+		CALC_IDLE,
+		CALC_READ,
+		CALC_PROCESS,	
+		CALC_WRITE
+	);
+	signal Calc_State : CalcState;
+
+	signal data_valid_ipcore : std_logic;
+	signal busy_ipcore : std_logic;
+	signal result_valid_ipcore : std_logic;
+
+	signal phase_ipcore : signed(31 downto 0); 
+	signal sine_ipcore : signed(31 downto 0);
+
+	
 begin
+	u_float_sine: entity work.float_sine
+		generic map(
+			ITERATIONS => 8
+		)
+		port map(
+			clk => clk,
+			reset => reset,
+
+			data_valid => data_valid_ipcore,
+			busy => busy_ipcore,
+			result_valid => result_valid_ipcore,
+			-- " TODO Check if this is allowed (direkt access to maped signal)"
+			angle => phase_ipcore,
+			sine => sine_ipcore
+		);
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -73,5 +105,6 @@ begin
     end process sync;
 
     task_state <= current_task_state;
+	phase_ipcore <= (SIGNED(phase));
 
 end architecture rtl;