Implemented Task Add in c an vhdl. Still testing

hardware/signal_processing/add.vhd

     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	signal start_ipcore : std_logic;
+	signal done_ipcore : std_logic;
+
+	signal a_readdata : std_logic_vector(31 downto 0);
+	signal b_readdata : std_logic_vector(31 downto 0);
+	signal result : std_logic_vector(31 downto 0);
+
+	type CalcState is (
+		CALC_IDLE,
+		CALC_READ,
+		CALC_PROCESS,	
+		CALC_WRITE
+	);
+	signal Calc_State : CalcState;
+
+
 begin
+	u_float_add: entity work.float_add
+		port map (
+			clk => clk,
+			reset => reset,
+			start => start_ipcore,
+			done => done_ipcore,
+			A => a_readdata,
+			B => b_readdata,
+			sum => result
+		);
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
                 if ( task_start = '1' ) then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
+
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
+
             when work.task.TASK_DONE =>
                 if ( task_start = '1' ) then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
+
         end case;
     end process task_state_transitions;
 
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
+			Calc_State <= CALC_IDLE;
             index <= 0;
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
-            when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
+				when work.task.TASK_IDLE =>
+					index <= 0;
+					Calc_State <= CALC_IDLE;
+					signal_write <= '0';
+
+				when work.task.TASK_RUNNING =>
+					case Calc_State is
+						when CALC_IDLE =>
+							Calc_State <= CALC_READ;
+						when CALC_READ =>
+							signal_write <= '0';
+							signal_a_read <= '1';
+							signal_b_read <= '1';
+							Calc_State <= CALC_PROCESS;
+						when CALC_PROCESS =>
+							signal_a_read <= '0';
+							signal_b_read <= '0';
+							start_ipcore <= '1';
+							if(done_ipcore = '1') then
+								start_ipcore <= '0';
+								Calc_State <= CALC_WRITE;
+							end if;
+						when CALC_WRITE =>
+							Calc_State <= CALC_READ;
+							index <= index + 1;
+							signal_write <= '1';
+					end case;
+
+				when work.task.TASK_DONE =>
+					index <= 0;
+					Calc_State <= CALC_IDLE;
+					signal_write <= '0';
+
             end case;
         end if;
     end process sync;
 
+	signal_writedata <= result;
+	a_readdata <= signal_a_readdata;
+	b_readdata <= signal_b_readdata;
+
     task_state <= current_task_state;
 
 end architecture rtl;

software/signal_processing/add.c

 #include "system/float_word.h"
 
 int task_add_run( void * task ) {
+	add_config* taskConfig = (add_config*) task;
 
-    // TODO
+	for(uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
+		float chnl1, chnl2;
+		data_channel_read(taskConfig->sources[0], (uint32_t*) &chnl1);
+		data_channel_read(taskConfig->sources[1], (uint32_t*) &chnl2);
+
+		float_word result;
+		result.value = chnl1 + chnl2;
+
+		data_channel_write(taskConfig->sink, result.word);
+	}
 
     return 0;
 }