signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

	signal start_ipcore : std_logic;
	signal done_ipcore : std_logic;

	signal a_readdata : std_logic_vector(31 downto 0);
	signal b_readdata : std_logic_vector(31 downto 0);
	signal result : std_logic_vector(31 downto 0);

	type CalcState is (
		CALC_IDLE,
		CALC_READ,
		CALC_PROCESS,	
		CALC_WRITE
	);
	signal Calc_State : CalcState;


begin
	u_float_add: entity work.float_add
		port map (
			clk => clk,
			reset => reset,
			start => start_ipcore,
			done => done_ipcore,
			A => a_readdata,
			B => b_readdata,
			sum => result
		);

    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;

            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;

            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;

        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
			Calc_State <= CALC_IDLE;
            index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
				when work.task.TASK_IDLE =>
					index <= 0;
					Calc_State <= CALC_IDLE;
					signal_write <= '0';

				when work.task.TASK_RUNNING =>
					case Calc_State is
						when CALC_IDLE =>
							Calc_State <= CALC_READ;
						when CALC_READ =>
							signal_write <= '0';
							signal_a_read <= '1';
							signal_b_read <= '1';
							Calc_State <= CALC_PROCESS;
						when CALC_PROCESS =>
							signal_a_read <= '0';
							signal_b_read <= '0';
							start_ipcore <= '1';
							if(done_ipcore = '1') then
								start_ipcore <= '0';
								Calc_State <= CALC_WRITE;
							end if;
						when CALC_WRITE =>
							Calc_State <= CALC_READ;
							index <= index + 1;
							signal_write <= '1';
					end case;

				when work.task.TASK_DONE =>
					index <= 0;
					Calc_State <= CALC_IDLE;
					signal_write <= '0';

            end case;
        end if;
    end process sync;

	signal_writedata <= result;
	a_readdata <= signal_a_readdata;
	b_readdata <= signal_b_readdata;

    task_state <= current_task_state;

end architecture rtl;